Coding for Computation: Efficient Compression of Neural Networks for Reconfigurable Hardware

2025-04-24

AI Summary

Neural network inference on reconfigurable hardware (e.g., FPGAs) suffers from high computational overhead—particularly in addition operations—while existing compression methods prioritize memory footprint reduction over computational efficiency. Method: This paper proposes a hardware-aware compression framework explicitly minimizing addition operations. It shifts the compression paradigm from weight storage optimization to critical-path computation optimization, introduces Linear Computation Coding (LCC)—a unified mechanism jointly regularizing pruning and quantization across training and inference—and designs an FPGA-aware inference scheduler. Contribution/Results: Evaluated on MLP and ResNet-34, the method achieves high accuracy while significantly reducing addition count, improving inference throughput and FPGA resource utilization. It establishes a new paradigm for hardware-efficient AI inference by co-optimizing algorithmic structure and hardware constraints.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Learning & Optimization for CV
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications

Abstract

As state of the art neural networks (NNs) continue to grow in size, their resource-efficient implementation becomes ever more important. In this paper, we introduce a compression scheme that reduces the number of computations required for NN inference on reconfigurable hardware such as FPGAs. This is achieved by combining pruning via regularized training, weight sharing and linear computation coding (LCC). Contrary to common NN compression techniques, where the objective is to reduce the memory used for storing the weights of the NNs, our approach is optimized to reduce the number of additions required for inference in a hardware-friendly manner. The proposed scheme achieves competitive performance for simple multilayer perceptrons, as well as for large scale deep NNs such as ResNet-34.

Problem

• Efficient compression of large neural networks
• Reduce computations for NN inference on FPGAs
• Hardware-friendly approach minimizing addition operations

Innovation

• Combines pruning, weight sharing, LCC
• Reduces additions for hardware efficiency
• Optimized for reconfigurable hardware like FPGAs