CLIPGen: A Chiplet Link IP Modeling and Generation Framework for 2.5D Architecture Exploration

2026-05-26

AI Summary

This work addresses the lack of an efficient exploration framework in early-stage 2.5D packaging design that jointly considers package and interconnect selection. It presents the first automated interface IP generation methodology enabling co-optimization of packaging and chiplet architectures. The proposed approach rapidly evaluates power, performance, and area across diverse 2.5D packaging and communication configurations, and automatically produces standard design assets—including Verilog, Liberty, LEF, and datasheets—that comply with protocols such as UCIe. By bridging the gap between high-fidelity and highly flexible interconnect modeling, this method significantly enhances the efficiency of system architecture exploration and the accuracy of design decisions.

Abstract

Advanced 2.5D Systems-in-Package (SiPs) compose a growing portion of high-performance systems. While the packaging and interconnect choices play a large role in the overall system design, system architects still lack a suitable framework for early design space exploration which takes these choices into account. Current interconnect models fall mostly into the categories of 1) detailed models which are generally inflexible and require deep packaging expertise, or 2) high-level models which don't provide enough information to make accurate architectural design decisions. In this work, we present an automated chiplet IP generation framework which provides power, performance, and area estimates for various 2.5D packaging and communication configurations. The IP generator produces standard collaterals required for high-level simulation/estimation, RTL simulation, and place-and-route-level implementation (Verilog, Liberty, LEF, and datasheet). Using our framework, architects can co-optimize the package and chiplet architecture through rapid power, performance, and area estimates of various packaging strategies. As a case study, we examine generated UCIe interfaces across several packaging options.

Problem

• 2.5D SiP
• chiplet
• interconnect modeling
• design space exploration
• packaging

Innovation

• Chiplet
• 2.5D Integration
• Interconnect Modeling
• Design Space Exploration
• UCIe