Context-aware Simopt-Power: Using structural data with simulation metadata to optimise FPGA designs

2026-05-23

AI Summary

This work addresses the inefficiency of traditional FPGA design flows, which neglect switching activity data from behavioral simulation and thus struggle to guide power optimization effectively. Existing approaches often rely on fixed thresholds or limited design awareness, incurring significant area overhead. To overcome these limitations, we propose Simopt-Power, a context-aware framework that integrates simulation-derived activity metadata with lightweight structural features—such as timing proximity, logic depth, and fanout—to accurately identify high-impact regions. Rather than using empirical tuning, our method incorporates architecture-aware parameters, including LUT size and mapping constraints, and jointly optimizes area-delay product (ADP) and power-delay product (PDP). Implemented within the open-source Yosys/ABC flow, Simopt-Power achieves an average 6.8% reduction in dynamic power on the Koios deep learning accelerator benchmark while limiting LUT area overhead to within 11.2%.

Abstract

Pre-implementation behavioural simulation routinely validates functional correctness, yet it also produces rich switching-activity traces that are typically discarded by FPGA computer-aided design (CAD) flows. Prior simulation-guided and power-aware FPGA optimisations demonstrate the promise of exploiting this metadata, but many rely on fixed thresholds, narrow decision heuristics, or limited design awareness, often incurring substantial area overhead. This paper presents Context-aware Simopt-Power, a simulator-guided optimisation framework that combines activity metadata with lightweight structural features (sequential proximity, logic-depth proxies, and fan-out estimates) to more precisely target high-impact regions of the netlist. We additionally remove empirically tuned constants, replacing them with architecture-aware parameters such as LUT size and mapping constraints, and evaluate trade-offs using power, delay, and a more useful metrics, area-delay product (AD) and power-delay product (PD). Implemented in an open-source Yosys/ABC flow and evaluated on the complex Koios deep-learning accelerator benchmarks, Context-aware Simopt-Power achieves an average 6.8% dynamic-power reduction while limiting LUT overhead to 11.2%, thus enabling a holistic design optimisation.

Problem

• FPGA optimization
• simulation metadata
• power-aware design
• context-aware optimization
• area overhead

Innovation

• context-aware optimization
• simulation-guided power reduction
• structural features
• FPGA CAD flow
• area-delay-power trade-off