🤖 AI Summary
In edge computing for multivariate time-series classification, conventional reservoir computing (RC) suffers from variable input lengths, resulting in non-fixed feature dimensions; existing intermediate representation (IR) methods rely on computationally expensive matrix inversion, hindering hardware deployment. Method: This paper proposes a dot-product-based fixed-dimensional intermediate representation (DPRR) and a fully digital delay-feedback reservoir (DFR), establishing the first purely digital RC architecture—eliminating analog circuitry and enabling high-level synthesis (HLS). DPRR achieves low-complexity, fixed-dimension feature compression via dot-product mapping, while DFR replaces analog dynamics with digital delay loops to drastically reduce hardware resource consumption. Contribution/Results: FPGA implementations across 12 standard benchmarks demonstrate superior classification accuracy over state-of-the-art methods, alongside 37–62% reduction in logic utilization—achieving a synergistic breakthrough in both accuracy and hardware efficiency.
📝 Abstract
Reservoir computing (RC) is attracting attention as a machine-learning technique for edge computing. In time-series classification tasks, the number of features obtained using a reservoir depends on the length of the input series. Therefore, the features must be converted to a constant-length intermediate representation (IR), such that they can be processed by an output layer. Existing conversion methods involve computationally expensive matrix inversion that significantly increases the circuit size and requires processing power when implemented in hardware. In this article, we propose a simple but effective IR, namely, dot-product-based reservoir representation (DPRR), for RC based on the dot product of data features. Additionally, we propose a hardware-friendly delayed-feedback reservoir (DFR) consisting of a nonlinear element and delayed feedback loop with DPRR. The proposed DFR successfully classified multivariate time series data that has been considered particularly difficult to implement efficiently in hardware. In contrast to conventional DFR models that require analog circuits, the proposed model can be implemented in a fully digital manner suitable for high-level syntheses. A comparison with existing machine-learning methods via field-programmable gate array implementation using 12 multivariate time-series classification tasks confirmed the superior accuracy and small circuit size of the proposed method.