Towards Optimal Circuit Generation: Multi-Agent Collaboration Meets Collective Intelligence

2025-04-20

AI Summary

Large language models (LLMs) generate digital circuits with significantly higher gate counts than human-designed counterparts (+38%–1075%), limiting practical adoption in hardware synthesis. Method: This paper introduces CircuitMind, a multi-agent framework integrating syntax-constrained decoding (restricting gate libraries), retrieval-augmented generation (RAG), and dual-objective reinforcement learning—jointly optimizing functional correctness and area efficiency. It pioneers a gate-level symbolic constraint decoding mechanism and establishes TC-Bench, the first collective-intelligence-driven gate-level benchmark, enriched with data from the TuringComplete ecosystem. Contribution/Results: Experiments show 55.6% of evaluated models match or surpass top human experts; the 14B Phi-4 model outperforms GPT-4o mini and Gemini 2.0 Flash, achieving top-quartile human-level area efficiency. This work marks the first demonstration of LLM-driven gate-level circuit synthesis competitive with expert human designers.

Technology Category

• Machine Learning: Large Multimodal Models (LMMs)
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Cognitive Modeling & Cognitive Systems: Agent Architectures

Application Category

• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Semantics and Knowledge: Data modeling to support human-machine intelligence, including LLMs agents, intelligent system behavior, explanations, and user-friendly interactions
• User Modeling, Personalization and Recommendation: Large Language Models (LLM) for user modeling and recommendation

Abstract

Large language models (LLMs) have transformed code generation, yet their application in hardware design produces gate counts 38%--1075% higher than human designs. We present CircuitMind, a multi-agent framework that achieves human-competitive efficiency through three key innovations: syntax locking (constraining generation to basic logic gates), retrieval-augmented generation (enabling knowledge-driven design), and dual-reward optimization (balancing correctness with efficiency). To evaluate our approach, we introduce TC-Bench, the first gate-level benchmark harnessing collective intelligence from the TuringComplete ecosystem -- a competitive circuit design platform with hundreds of thousands of players. Experiments show CircuitMind enables 55.6% of model implementations to match or exceed top-tier human experts in composite efficiency metrics. Most remarkably, our framework elevates the 14B Phi-4 model to outperform both GPT-4o mini and Gemini 2.0 Flash, achieving efficiency comparable to the top 25% of human experts without requiring specialized training. These innovations establish a new paradigm for hardware optimization where collaborative AI systems leverage collective human expertise to achieve optimal circuit designs. Our model, data, and code are open-source at https://github.com/BUAA-CLab/CircuitMind.

Problem

• Reducing gate counts in hardware design using LLMs
• Achieving human-competitive circuit design efficiency
• Leveraging collective intelligence for optimal circuit generation

Innovation

• Syntax locking for basic logic gates
• Retrieval-augmented generation for knowledge-driven design
• Dual-reward optimization balancing correctness and efficiency