EEspice: A Modular Circuit Simulation Platform with Parallel Device Model Evaluation via Graph Coloring

2026-04-03

AI Summary

This work addresses the high computational cost of nonlinear device models—such as BSIM—in traditional circuit simulation and the performance bottleneck caused by write conflicts in shared matrices during parallel execution. The authors propose a graph coloring–based parallel stamping strategy that partitions MOSFET instances into conflict-free color groups, enabling efficient concurrent evaluation of device models and matrix assembly. By employing a modular kernel design with a replaceable architecture, the approach decouples device model computations, substantially alleviating contention among multiple cores during writes to shared data structures. Experimental results on a 64-core workstation demonstrate a speedup of up to 45× over a single-threaded implementation in low-conflict scenarios.

Technology Category

• Machine Learning: Hardware-aware ML
• Data Mining & Knowledge Management: Scalability, Parallel & Distributed Systems
• Search and Optimization: Sampling/Simulation-based Search

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Security and Privacy: Large-scale security measurements
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization

Abstract

As modern analogue/mixed-signal design increasingly relies on optimization-in-the-loop flows, such as AI and LLM-based sizing agents that repeatedly invoke SPICE-efficient, accurate high-performance simulators have become an indispensable foundation for modern integrated circuit (IC) design. However, the computational cost of evaluating nonlinear models, particularly for BSIM models, remains a significant bottleneck. In standard parallelization approaches, devices such as transistors are easily distributed across processors. The subsequent stamping phase, where each device's contributions are added to the shared system matrix, often creates a bottleneck. Because multiple processor cores compete to update the same matrix elements simultaneously, the system is forced to process tasks one at a time to avoid errors. This paper introduces EEspice, an open-source circuit simulation framework whose modular architecture decouples device model evaluation into independently replaceable kernels, enabling a parallel stamping strategy that overcomes this bottleneck. It partitions MOSFET instances into independent color groups, which can be processed in parallel. Our results show that on a 64-core workstation, the proposed approach achieves up to 45x speedup over single-thread performance when conflicts are low. Our analysis also explores how performance depends on circuit topology.

Problem

• circuit simulation
• parallelization bottleneck
• device model evaluation
• matrix stamping
• BSIM models

Innovation

• parallel stamping
• graph coloring
• modular simulation
• device model evaluation
• circuit simulation