🤖 AI Summary
To address the lack of explicit temporal semantics and execution-order modeling in functional languages for high-level synthesis (HLS), this paper proposes a novel hardware description methodology integrating the Synchronous Dataflow with Actor Parameters (SDF-AP) model and Template Haskell. It is the first to embed SDF-AP’s production/consumption timing constraints directly into functional specifications, leveraging higher-order function reuse and dataflow patterns to jointly characterize resource allocation and critical-path latency. Built upon the Clash compiler framework, the approach automatically generates VHDL/Verilog code featuring deterministic timing behavior and complete control- and data-path implementations. Experimental evaluation across multiple benchmarks demonstrates stable resource utilization and strict cycle-accurate timing predictability. Compared to Vitis HLS, the method achieves 23–41% average latency reduction and up to 18% lower resource consumption in selected designs.
📝 Abstract
Functional languages as input specifications for High-Level Synthesis (HLS) tools allow to specify data dependencies but do not contain a notion of time nor execution order. In this paper, we propose a method to add this notion to the functional description using the dataflow model SDF-AP. SDF-AP consists of patterns that express consumption and production that we can use to enforce resource usage. We created an HLS-tool that can synthesize parallel hardware, both data and control path, based on the repetition, expressed in Higher-Order Functions, combined with specified SDF-AP patterns. Our HLS-tool, based on Template Haskell, generates an Abstract Syntax Tree based on the given patterns and the functional description uses the Clash-compiler to generate VHDL/Verilog. Case studies show consistent resource consumption and temporal behavior for our HLS. A comparison with a commercially available HLS-tool shows that our HLS tool outperforms in terms of latency and sometimes in resource consumption. The method and tool presented in this paper offer more transparency to the developer and allow to specify more accurately the synthesized hardware compared to what is possible with pragmas of the Vitis HLS-tool.