ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips

2024-09-04

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

AI Summary

To address the insufficient resilience of integrated circuits against distributed, regional, and composite attacks in untrusted supply chains, this paper proposes a “composability-driven diversity” design paradigm. Our approach leverages modular composability and E-Graph–based gate-level rewriting to jointly achieve fine-grained logical diversity and coarse-grained module-level redundancy—without introducing additional spatial overhead. Compared with conventional redundancy-based schemes, the proposed method maintains bounded area cost while improving average attack resilience by 5× across all three attack classes. Experimental evaluation demonstrates its feasibility for efficiently constructing high-resilience secure chips in untrusted supply chain environments. This work establishes a novel hardware security design methodology for the post-Moore era, advancing resilient chip design under supply chain threats.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Computer Vision: Adversarial Attacks & Robustness

Application Category

• Security and Privacy: Large-scale security measurements
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems

Abstract

A long-standing challenge is the design of chips resilient to faults and glitches. Both fine-grained gate diversity and coarse-grained modular redundancy have been used in the past. However, these approaches have not been well-studied under other threat models where some stakeholders in the supply chain are untrusted. Increasing digital sovereignty tensions raise concerns regarding the use of foreign off-the-shelf tools and IPs, or off-sourcing fabrication, driving research into the design of resilient chips under this threat model. This paper addresses a threat model considering three pertinent attacks to resilience: distribution, zonal, and compound attacks. To mitigate these attacks, we introduce the exttt{ResiLogic} framework that exploits extit{Diversity by Composability}: constructing diverse circuits composed of smaller diverse ones by design. This gives designer the capability to create circuits at design time without requiring extra redundancy in space or cost. Using this approach at different levels of granularity is shown to improve the resilience of circuit design in exttt{ResiLogic} against the three considered attacks by a factor of five. Additionally, we also make a case to show how E-Graphs can be utilized to generate diverse circuits under given rewrite rules.

Problem

• Design chips resilient to faults and glitches
• Address threats from untrusted supply chain stakeholders
• Mitigate distribution, zonal, and compound attacks

Innovation

• Leveraging composability for diverse circuit design
• Using E-Graphs to generate diverse circuits
• Improving resilience against multiple attack types