ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training

2026-06-04

AI Summary

This work addresses the high computational cost and energy consumption in on-chip training of spiking neural networks (SNNs), primarily caused by the massive number of synaptic weight updates. To overcome this challenge, the authors propose an endogenous timing-based power-of-two STDP learning mechanism (ITP-STDP) along with a dedicated hardware architecture, which for the first time integrates endogenous timing dynamics with power-of-two quantization to eliminate computational redundancy through algorithm-hardware co-design. Guided by dynamical analysis based on a mean-field synaptic drift model, an efficient weight-update strategy is devised. Experimental results demonstrate that the FPGA implementation achieves 4.5–219.8× higher energy efficiency, while the ASIC realization delivers 4.8–22.01× speedup with only 1.2%–3.3% of the area required by prior designs.

Abstract

Spiking neural networks (SNNs) have the potential to emerge as the third generation of neural networks and have attracted increasing attention across a wide range of applications. However, the large number of synaptic connections in SNNs leads to intensive weight-update computation by on-chip learning algorithms during training, resulting in substantial hardware resource utilization and energy consumption. Among existing SNN learning algorithms, spike-timing-dependent plasticity (STDP) is one of the most extensively studied and widely adopted, serving as a fundamental learning component in SNNs. To address the hardware and energy overheads associated with SNN training, this paper presents intrinsic-timing power-of-two STDP (ITP-STDP) and its corresponding prototype learning engine hardware architecture. The proposed design is evaluated through a dedicated mean-field synaptic drift model for dynamical analysis and further validated across SNN networks of different scales and datasets. It is further implemented on both ASIC and FPGA platforms and compared with state-of-the-art approaches, including the original STDP and more complex STDP variants. The results demonstrate superior energy efficiency, higher operating speed, and substantially lower hardware resource utilization, as the proposed design eliminates most of the computational overhead of STDP through both algorithmic and hardware-level optimizations. On the FPGA platform, the proposed design improves energy efficiency by 4.5$\times$ to 219.8$\times$ over the compared designs. On the ASIC platform, the proposed design achieves a 4.8$\times$ to 22.01$\times$ speedup while consuming only 1.2% to 3.3% of the area required by prior works.

Problem

• Spiking Neural Networks
• On-chip Learning
• STDP
• Hardware Overhead
• Energy Efficiency

Innovation

• ITP-STDP
• Spiking Neural Networks
• On-chip Learning
• Energy Efficiency
• Hardware Optimization