A Unified Hardware Accelerator for Fast Fourier Transform and Number Theoretic Transform

2025-04-06

IEEE International Conference on Acoustics, Speech, and Signal Processing

AI Summary

To address resource redundancy arising from separate hardware implementations of FFT (for digital signal processing) and NTT (for post-quantum cryptographic polynomial multiplication), this paper proposes a deeply unified hardware accelerator architecture. The design supports both 512-point complex FFT and 256-point NTT, targeting NIST-standardized PQC schemes (e.g., ML-KEM/ML-DSA) and general-purpose DSP applications. Its key innovation lies in the first-of-its-kind deep sharing of butterfly computation units, data paths, and control logic between FFT and NTT—achieved solely by integrating a lightweight modular reduction circuit and reconfiguring the control finite-state machine for dual-domain compatibility. Implemented on FPGA, the unified accelerator delivers performance comparable to dedicated NTT accelerators while significantly reducing area overhead. Experimental results validate its feasibility and efficiency for practical PQC deployment and multi-domain signal processing.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Non-convex Optimization
• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures

Application Category

• Security and Privacy: Applications of cryptography
• Systems and Infrastructure for Web, Mobile and WoT: Federated Web and WoT systems, including distributed, federated and edge-based data processing
• Search and Retrieval-Augmented AI: Retrieval-Augmented Generation (RAG) and multi-modal RAG

Abstract

The Number Theoretic Transform (NTT) is an indispensable tool for computing efficient polynomial multiplications in post-quantum lattice-based cryptography. It has strong resemblance with the Fast Fourier Transform (FFT), which is the most widely used algorithm in digital signal processing. In this work, we demonstrate a unified hardware accelerator supporting both 512-point complex FFT as well as 256-point NTT for the recently standardized NIST post-quantum key encapsulation and digital signature algorithms ML-KEM and ML-DSA respectively. Our proposed architecture effectively utilizes the arithmetic circuitry required for complex FFT, and the only additional circuits required are for modular reduction along with modifications in the control logic. Our implementation achieves performance comparable to state-of-the-art ML-KEM / ML-DSA NTT accelerators on FPGA, thus demonstrating how an FFT accelerator can be augmented to support NTT and the unified hardware can be used for both digital signal processing and post-quantum lattice-based cryptography applications.

Problem

• Unified hardware for FFT and NTT computations
• Supporting post-quantum cryptography and signal processing
• Efficiently combining arithmetic circuits for both transforms

Innovation

• Unified hardware accelerator for FFT and NTT
• Reuses FFT circuitry with modular reduction
• Supports both DSP and post-quantum cryptography