Leveraging Application-Specific Knowledge for Energy-Efficient Deep Learning Accelerators on Resource-Constrained FPGAs

2025-04-12

AI Summary

To address the low energy efficiency and poor adaptability of deploying deep learning models on resource-constrained FPGAs in IoT edge scenarios, this paper proposes a co-optimized, automated accelerator generation methodology. Our approach systematically embeds application-specific knowledge into the RTL synthesis flow for the first time, jointly optimizing RTL-level customization, load-aware scheduling, and semantics-aware mapping. Guided by design space exploration (DSE), the automated framework achieves joint optimization of energy efficiency and real-time performance under strict hardware resource constraints. Evaluated on Xilinx UltraScale+ FPGAs, the generated accelerators achieve an average 2.3× improvement in energy efficiency over baseline implementations, meet real-time inference latency requirements, and maintain FPGA resource utilization at or below 92%.

Technology Category

• Machine Learning: Hardware-aware ML
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Search and Optimization: Learning to Search

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• User Modeling, Personalization and Recommendation: Federated recommendation systems and personalization
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

The growing adoption of Deep Learning (DL) applications in the Internet of Things has increased the demand for energy-efficient accelerators. Field Programmable Gate Arrays (FPGAs) offer a promising platform for such acceleration due to their flexibility and power efficiency. However, deploying DL models on resource-constrained FPGAs remains challenging because of limited resources, workload variability, and the need for energy-efficient operation. This paper presents a framework for generating energy-efficient DL accelerators on resource-constrained FPGAs. The framework systematically explores design configurations to enhance energy efficiency while meeting requirements for resource utilization and inference performance in diverse application scenarios. The contributions of this work include: (1) analyzing challenges in achieving energy efficiency on resource-constrained FPGAs; (2) proposing a methodology for designing DL accelerators with integrated Register Transfer Level (RTL) optimizations, workload-aware strategies, and application-specific knowledge; and (3) conducting a literature review to identify gaps and demonstrate the necessity of this work.

Problem

• Energy-efficient DL accelerators on resource-constrained FPGAs
• Optimizing design configurations for energy efficiency
• Addressing workload variability and resource limitations

Innovation

• Energy-efficient DL accelerators on FPGAs
• RTL optimizations and workload-aware strategies
• Application-specific knowledge integration