Accelerating Hybrid XOR$-$CNF SAT Problems Natively with In-Memory Computing

2025-04-08

AI Summary

To address the low efficiency of solving XOR-CNF hybrid Boolean satisfiability (SAT) problems—arising in cryptanalysis, circuit design, and related domains—this paper proposes the first in-memory computing hardware accelerator specifically designed for joint XOR-CNF constraints. Built upon memristor crossbar arrays, the architecture natively supports co-encoding and parallel solving of XOR and CNF clauses, eliminating the overhead of conventional conversion to pure CNF. Custom in-memory logic operations and algorithm-hardware co-optimization further enhance execution efficiency. Experimental results demonstrate that, compared to state-of-the-art CNF-conversion-based approaches, the proposed accelerator achieves approximately 10× improvements in solving speed, energy efficiency, and chip area utilization. Against advanced CPU-based SAT solvers, it delivers a 10× speedup and a three-order-of-magnitude improvement in energy efficiency.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Satisfiability
• Search and Optimization: Mixed Discrete/Continuous Search

Application Category

• Security and Privacy: Applications of cryptography
• Search and Retrieval-Augmented AI: Vertical and domain-specific search
• Responsible Web: Measurement, analysis, and circumvention of Web censorship

Abstract

The Boolean satisfiability (SAT) problem is a computationally challenging decision problem central to many industrial applications. For SAT problems in cryptanalysis, circuit design, and telecommunication, solutions can often be found more efficiently by representing them with a combination of exclusive OR (XOR) and conjunctive normal form (CNF) clauses. We propose a hardware accelerator architecture that natively embeds and solves such hybrid CNF$-$XOR problems using in-memory computing hardware. To achieve this, we introduce an algorithm and demonstrate, both experimentally and through simulations, how it can be efficiently implemented with memristor crossbar arrays. Compared to the conventional approaches that translate CNF$-$XOR problems to pure CNF problems, our simulations show that the accelerator improves computation speed, energy efficiency, and chip area utilization by $sim$10$ imes$ for a set of hard cryptographic benchmarking problems. Moreover, the accelerator achieves a $sim$10$ imes$ speedup and a $sim$1000$ imes$ gain in energy efficiency over state-of-the-art SAT solvers running on CPUs.

Problem

• Accelerates hybrid CNF-XOR SAT problems efficiently
• Uses in-memory computing for faster solutions
• Improves speed and energy efficiency significantly

Innovation

• In-memory computing for hybrid CNF-XOR problems
• Memristor crossbar arrays implementation
• 10x speedup and 1000x energy efficiency