Introducing the Arm-membench Throughput Benchmark

2025-04-09

AI Summary

Modern processors are often limited by memory subsystem performance rather than computational throughput, yet existing benchmarks inadequately capture the interplay between memory accesses and compute instructions in determining real-world throughput. To address this, we design and implement Arm-membench—the first fine-grained memory bandwidth benchmark for the Armv8 architecture, fully supporting all current SIMD extensions—and achieve the first complete port and deep optimization of x86-membench to Arm. Leveraging Armv8 ISA modeling, custom SIMD assembly micro-benchmarks, and multi-core microarchitectural analysis, we uncover a previously unreported bottleneck: instruction fetch and decode width becomes critical under memory-intensive workloads. Empirical evaluation on Fujitsu A64FX, Ampere Altra, and Cavium ThunderX2 demonstrates that Arm-membench precisely quantifies pipeline-level bottlenecks under cache-bandwidth constraints, providing a novel methodology for performance modeling and microarchitectural analysis on Arm platforms.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Search and Optimization: Evaluation and Analysis

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Security and Privacy: Large-scale security measurements
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics

Abstract

Application performance of modern day processors is often limited by the memory subsystem rather than actual compute capabilities. Therefore, data throughput specifications play a key role in modeling application performance and determining possible bottlenecks. However, while peak instruction throughputs and bandwidths for local caches are often documented, the achievable throughput can also depend on the relation between memory access and compute instructions. In this paper, we present an Arm version of the well established x86-membench throughput benchmark, which we have adapted to support all current SIMD extensions of the Armv8 instruction set architecture. We describe aspects of the Armv8 ISA that need to be considered in the portable design of this benchmark. We use the benchmark to analyze the memory subsystem at a fine spatial granularity and to unveil microarchitectural details of three processors: Fujitsu A64FX, Ampere Altra and Cavium ThunderX2. Based on the resulting performance information, we show that instruction fetch and decoder widths become a potential bottleneck for cache-bandwidth-sensitive workloads due to the load-store concept of the Arm ISA.

Problem

• Assessing memory subsystem impact on processor performance
• Adapting x86-membench for Armv8 SIMD extensions
• Analyzing microarchitectural details of Arm processors

Innovation

• Adapted x86-membench for Armv8 SIMD extensions
• Analyzed memory subsystem at fine granularity
• Revealed instruction fetch bottleneck in Arm ISA