CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor

2025-04-08

AI Summary

To address the unpredictability of virtual memory access latency, severe shared-resource interference, and high area/performance overheads of existing solutions for the RISC-V CVA6 processor in real-time virtualization, this paper proposes a predictability-oriented virtual memory architecture. Our approach introduces three key innovations: (1) a dynamically partitioned TLB enabling per-thread static TLB entry overwriting and deterministic address translation; (2) a hybrid L1 cache/scratchpad memory (SPM) architecture supporting fine-grained, runtime-configurable cache-SPM resource allocation; and (3) hardware-assisted, OS-coordinated static TLB management combined with virtualization interference isolation. Evaluation under heavy interference shows that worst-case execution time (WCET) predictability for critical tasks improves by 94%, with only a 4% area overhead, no timing penalty, and negligible performance impact on non-critical tasks.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• Responsible Web: Data and user privacy-enhancing technologies for the Web
• Security and Privacy: Large-scale security measurements

Abstract

The increasing complexity of autonomous systems has driven a shift to integrated heterogeneous SoCs with real-time and safety demands. Ensuring deterministic WCETs and low-latency for critical tasks requires minimizing interference on shared resources like virtual memory. Existing techniques, such as software coloring and memory replication, introduce significant area and performance overhead, especially with virtualized memory where address translation adds latency uncertainty. To address these limitations, we propose CVA6-VMRT, an extension of the open-source RISC-V CVA6 core, adding hardware support for predictability in virtual memory access with minimal area overhead. CVA6-VMRT features dynamically partitioned Translation Look-aside Buffers (TLBs) and hybrid L1 cache/scratchpad memory (SPM) functionality. It allows fine-grained per-thread control of resources, enabling the operating system to manage TLB replacements, including static overwrites, to ensure single-cycle address translation for critical memory regions. Additionally, CVA6-VMRT enables runtime partitioning of data and instruction caches into cache and SPM sections, providing low and predictable access times for critical data without impacting other accesses. In a virtualized setting, CVA6-VMRT enhances execution time determinism for critical guests by 94% during interference from non-critical guests, with minimal impact on their average absolute execution time compared to isolated execution of the critical guests only. This interference-aware behaviour is achieved with just a 4% area overhead and no timing penalty compared to the baseline CVA6 core.

Problem

• Ensures deterministic WCETs in RISC-V processors
• Minimizes virtual memory access latency uncertainty
• Reduces interference on shared memory resources

Innovation

• Dynamically partitioned TLBs for predictable access
• Hybrid L1 cache/scratchpad memory functionality
• Runtime cache/SPM partitioning for low latency