Fast Thermal-Aware Chiplet Placement Assisted by Surrogate

2025-04-04

AI Summary

To address the high computational overhead and the coupled wirelength–temperature optimization challenge in thermal-aware chiplet placement for 2.5D advanced packaging, this paper proposes a novel thermal-aware placement method integrating Radial Basis Function (RBF) surrogate modeling with simulated annealing. The RBF network is innovatively embedded within the optimization framework to jointly enable rapid thermal field approximation and efficient layout convergence. This approach significantly reduces thermal simulation cost while maintaining accuracy. Experimental evaluation on multiple benchmark circuits demonstrates an average peak temperature reduction of 8.2% and a 3.1× acceleration in placement convergence speed, compared to state-of-the-art methods. Moreover, the proposed method achieves a superior trade-off between wirelength and thermal performance, attaining internationally competitive levels in comprehensive thermal–electrical co-optimization metrics.

Technology Category

• Machine Learning: Hardware-aware ML
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Search and Optimization: Sampling/Simulation-based Search

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments

Abstract

With the advent of the post-Moore era, the 2.5-D advanced package is a promising solution to sustain the development of very large-scale integrated circuits. However, the thermal placement of chiplet, due to the high complexity of thermal simulation, is very challenging. In this paper, a surrogate-assisted simulated annealing algorithm is proposed to simultaneously minimize both the wirelength and the maximum temperature of integrated chips. To alleviate the computational cost of thermal simulation, a radial basis function network is introduced to approximate the thermal field, assisted by which the simulated annealing algorithm converges to the better placement in less time. Numerical results demonstrate that the surrogate-assisted simulated annealing algorithm is competitive to the state-of-the-art thermal placement algorithms of chiplet, suggesting its potential application in the agile design of 2.5D package chip.

Problem

• Minimize wirelength and chip temperature in 2.5D placement
• Reduce thermal simulation complexity with surrogate modeling
• Accelerate chiplet placement using surrogate-assisted simulated annealing

Innovation

• Surrogate-assisted simulated annealing algorithm
• Radial basis function approximates thermal field
• Minimizes wirelength and maximum temperature