Reconfigurable Time-Domain In-Memory Computing Marco using CAM FeFET with Multilevel Delay Calibration in 28 nm CMOS

2025-04-04

AI Summary

This work addresses key challenges in in-memory computing (IMC), including high data movement overhead, excessive analog-to-digital converter (ADC) power consumption, and limited temporal resolution in time-domain architectures. To this end, we propose a reconfigurable time-domain non-volatile IMC (TD-nvIMC) accelerator fabricated in 28 nm CMOS and integrated with ferroelectric field-effect transistor (FeFET) non-volatile memory. By employing time-domain encoding for binary multiply-accumulate (MAC) operations, the design eliminates the need for conventional ADCs. It achieves, for the first time, FeFET-based in-memory computation with a 550 ps time-step resolution; introduces a multi-level state isolation body technique to suppress write disturbance; and incorporates an on-chip multi-stage delay calibration circuit, improving temporal resolution to 100 ps. Experimental results demonstrate a peak throughput of 232 GOPS and energy efficiency of 1887 TOPS/W at 0.85 V, with time-domain precision improved by approximately 2000× over prior art.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Application Domains: Internet of Things, Sensor Networks & Smart Cities

Application Category

• Search and Retrieval-Augmented AI: Vertical and domain-specific search
• User Modeling, Personalization and Recommendation: On-Device user modeling, personalization, and recommendation
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization

Abstract

Time-domain nonvolatile in-memory computing (TD-nvIMC) architectures enhance energy efficiency by reducing data movement and data converter power. This work presents a reconfigurable TD-nvIMC accelerator integrating on-die a ferroelectric FET content-addressable memory array, delay element chain, and time-to-digital converter. Fabricated in 28 nm CMOS, it supports binary MAC operations using XOR/AND for multiplication and Boolean logic. FeFET-based nvIMC with 550 ps step size is empirically demonstrated, almost 2000$ imes$ improvement from previous works. Write-disturb prevention and multilevel state (MLS) is demonstrated using isolated bulks. Delay element mismatch is compensated through an on-die MLS calibration for robust operation with a high temporal resolution of 100 ps. The proposed architecture can achieve a throughput of 232 GOPS and energy efficiency of 1887 TOPS/W with a 0.85-V supply, making it a promising candidate for efficient in-memory computing.

Problem

• Enhancing energy efficiency in in-memory computing architectures
• Integrating FeFET CAM array for reconfigurable TD-nvIMC acceleration
• Compensating delay element mismatch with multilevel calibration

Innovation

• FeFET-based nvIMC with 550 ps step
• On-die MLS calibration for 100 ps resolution
• Reconfigurable TD-nvIMC accelerator in 28 nm CMOS