Hermes: A Unified High-Performance NTT Architecture with Hybrid Dataflow

2026-03-02

AI Summary

In hybrid homomorphic encryption (HHE), multi-length number-theoretic transform (NTT) computations pose a significant performance bottleneck due to their computational intensity and the lack of unified hardware support. This work proposes Hermes, the first unified NTT acceleration architecture tailored for HHE. Hermes integrates a fully pipelined on-chip compute core, spatiotemporal parallelism, a conflict-free on-chip tiling algorithm, and a hybrid dataflow design to substantially enhance computational intensity while reducing bandwidth demands. By further leveraging optimized HBM burst accesses and data reuse strategies, Hermes achieves high throughput across diverse NTT lengths, outperforming state-of-the-art GPU and FPGA accelerators by 13.6× and 1.3×, respectively.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Heuristic Search
• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures

Application Category

• Security and Privacy: Applications of cryptography
• Graph Algorithms and Modeling for the Web: Algorithms and analysis for heterogeneous, signed, attributed, multi-relational, temporal, higher-order, and annotated Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications

Abstract

Fully Homomorphic Encryption (FHE) relies heavily on the Number Theoretic Transform (NTT), making NTT a major performance bottleneck due to its intensive polynomial computations. Hybrid Homomorphic Encryption (HHE), which integrates arithmetic and logic FHE, further requires support for multiple NTT lengths. However, existing accelerators mainly optimize NTT throughput and do not provide unified support for HHE. This paper presents Hermes, a unified high-performance NTT architecture based on hybrid dataflow. Hermes exploits parallelism along both temporal and spatial dimensions and incorporates a fully pipelined on-chip computing core. A conflict-free on-chip fragmentation algorithm is introduced to resolve bank conflicts and enable burst HBM access, while an efficient dataflow improves computational intensity through data reuse, reducing bandwidth demand. Experimental results show that Hermes supports multiple NTT lengths and achieves up to 13.6x and 1.3x higher throughput than state-of-the-art GPU and FPGA accelerators, respectively. Our source code is available at https://anonymous.4open.science/r/Hermes_conf-4E6F.

Problem

• Fully Homomorphic Encryption
• Hybrid Homomorphic Encryption
• Number Theoretic Transform
• NTT acceleration
• hardware architecture

Innovation

• Number Theoretic Transform (NTT)
• Hybrid Dataflow
• Fully Homomorphic Encryption (FHE)
• Conflict-Free Memory Access
• High-Performance Accelerator