Capstone: Power-Capped Pipelining for Coarse-Grained Reconfigurable Array Compilers

2026-02-28

AI Summary

This work addresses the challenge that modern CGRA compilers often violate hard power constraints when applying aggressive pipelining optimizations. To this end, it introduces the first approach that directly embeds a user-specified power budget into the CGRA bitstream selection process. Building upon the Cascade compiler framework, the method integrates an intrinsic fast power model and a tunable controller to prune configurations exceeding the power limit during post-place-and-route stages. Evaluated across diverse dense and sparse computational kernels, the proposed technique effectively enforces power compliance, substantially reduces power margin overhead, and maximizes safe operating frequency—thereby enabling high-performance compilation under strict power constraints.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Computer Vision: Computational Photography, Image & Video Synthesis

Application Category

• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Security and Privacy: Large-scale security measurements

Abstract

Coarse-grained reconfigurable arrays (CGRAs) have attracted growing interest because they exhibit performance and energy efficiency competitive with ASICs while maintaining flexibility similar to FPGAs. These properties make CGRAs attractive in accelerator and other power-constrained system contexts. However, modern CGRA compilers aggressively pipeline for frequency and performance improvements, often violating hard power budgets. We empirically show that, in state-of-the-art CGRA compilers such as Cascade, post-place-and-route (post-PnR) pipelining increases power monotonically and ultimately exceeds fixed power caps across diverse workloads. In response, we introduce \emph{Capstone}, a power-aware extension of Cascade that integrates a fast, compiler-resident power model with a user-tunable controller that guides the bitstream selection process towards optimization targets. Capstone predicts per-iteration power directly inside the post-PnR compilation loop and selects one or a small set of PnR configurations such that at least one meets a user-specified power cap. Thus, we shift the objective from indiscriminately maximizing frequency to maximizing safe frequency under a discrete power cap. On a suite of kernels spanning fundamental dense and sparse applications, Capstone meets a power cap and minimizes remaining power headroom while preserving feasible performance. Our results indicate that cap-aware compilation is both necessary and practical, as the compiler can proactively land on cap-compliant points and expose predictable performance under power constraints.

Problem

• Coarse-Grained Reconfigurable Array
• Power Capping
• Compiler
• Pipelining
• Power Budget

Innovation

• power-capped pipelining
• coarse-grained reconfigurable array (CGRA)
• compiler-aware power modeling
• post-place-and-route optimization
• cap-compliant compilation