pc-COP: An Efficient and Configurable 2048-p-Bit Fully-Connected Probabilistic Computing Accelerator for Combinatorial Optimization

2024-09-23

IEEE Conference on High Performance Extreme Computing

AI Summary

For NP-hard combinatorial optimization problems (e.g., Max-Cut), this work proposes a probabilistic computing hardware accelerator tailored for FPGAs. The design centers on a 2048-node fully connected p-bit array and introduces two key innovations: a pseudo-parallel p-bit update architecture and a novel speculate-and-select hardware logic unit. Implemented on a Xilinx UltraScale+ FPGA, the accelerator achieves co-optimized high throughput and low resource utilization. Compared to state-of-the-art approaches, it delivers a 4× speedup while attaining an average accuracy of 99% on the G-Set benchmark—matching SOTA accuracy—yet reduces LUT and BRAM consumption significantly. The architecture is highly efficient, configurable, and scalable across hardware platforms, enabling practical deployment of probabilistic computing for large-scale optimization.

Technology Category

• Machine Learning: Probabilistic Circuits and Graphical Models
• Search and Optimization: Combinatorial Optimization
• Reasoning under Uncertainty: Stochastic Optimization

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

Probabilistic computing is an emerging quantum-inspired computing paradigm capable of solving combinatorial optimization and various other classes of computationally hard problems. In this work, we present pc-COP, an efficient and configurable probabilistic computing hardware accelerator with 2048 fully connected probabilistic bits (p-bits) implemented on Xilinx UltraScale+ FPGA. We propose a pseudo-parallel p-bit update architecture with speculate-and-select logic which improves overall performance by 4 x compared to the traditional sequential p-bit update. Using our FPGA-based accelerator, we demonstrate the standard G-Set graph maximum cut benchmarks with near-99% average accuracy. Compared to state-of-the-art hardware implementations, we achieve similar performance and accuracy with lower FPGA resource utilization.

Problem

• Develops a 2048-p-bit probabilistic computing accelerator for optimization
• Enhances performance via pseudo-parallel p-bit update architecture
• Achieves high accuracy in G-Set benchmarks with lower resource use

Innovation

• 2048 fully connected p-bits on FPGA
• Pseudo-parallel p-bit update architecture
• Speculate-and-select logic for 4x speedup