DTCO Exploration of NOR-Type IGZO FeFETs for Read-Dominated Memories

2026-04-15

AI Summary

This study addresses critical challenges in NOR-type IGZO ferroelectric field-effect transistors (FeFETs) for AI inference memory, including write difficulty, read disturbance, and 3D stacking leakage currents. Through design-technology co-optimization (DTCO) and back-end-of-line (BEOL) integration, the work systematically evaluates area scalability, read latency, and array-level read margin. It reveals, for the first time, a read suppression mechanism induced by negative programmed-state threshold voltage and mitigates it via positive threshold voltage engineering, such as ferroelectric layer thinning. The study also uncovers a new mechanism wherein inter-cell leakage current fundamentally limits 3D FeNOR stacking density. At the 7 nm node, the proposed approach achieves a bitcell area of 0.016 μm²—equivalent to a 10T SRAM—and sub-5 ns random access latency, while identifying key process pathways essential for enhancing read margin.

Technology Category

• Machine Learning: Hardware-aware ML
• Natural Language Processing: Learning & Optimization for NLP
• Search and Optimization: Learning to Search

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Security and Privacy: Large-scale security measurements
• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs

Abstract

InGaZnO (IGZO) channel FeFETs have attracted notable interest thanks to their advances in endurance. This work evaluates the viability of NOR-type IGZO FeFETs for readcentric AI inference workloads via design-technology cooptimization (DTCO). We demonstrate the cross-node bitcell footprint scalability of back-end-of-line (BEOL) IGZO FeFETs capable of delivering 10-A SRAM-equivalent area (0.016 um2) with 7-nm ground rules and reaching sub-5 ns random access latency despite writability challenges. We further identify the sensing margin penalty in NOR FeFET arrays arising from sneak current associated with the negative program-state Vt, which requires positive-Vt engineering in order to eliminate the unwanted negative voltage read inhibition - for example, by ferroelectric layer thinning. Last but not least, we elucidate the read margin implications on 3D FeNOR for storage-class memories (SCMs), with the 3D stacking density limited by additional sneak current from neighbor channel shunting.

Problem

• FeFET
• IGZO
• read margin
• sneak current
• 3D stacking

Innovation

• IGZO FeFET
• DTCO
• NOR memory
• sneak current
• 3D stacking