Ferroelectric FET-based Logic-in-Memory Encoder for Hyperdimensional Computing

2025-12-23

AI Summary

To address the area, energy, and latency bottlenecks of high-dimensional encoders in applications such as language identification and DNA sequencing, this work proposes an in-memory logic encoding architecture built upon a single fully depleted silicon-on-insulator (FDSOI) ferroelectric field-effect transistor (FeFET). It is the first demonstration of FeFETs implementing XOR and three-input majority gates to enable N-gram high-dimensional encoding. Departing from conventional ternary content-addressable memory (TCAM)-based acceleration, the architecture is co-designed for encoding-centric workloads. Through device-level modeling, in-memory Boolean logic design, hardware mapping, and integration into an SMS spam classification accelerator, the system achieves 91.38% classification accuracy on the SMS Spam Collection dataset. Compared to state-of-the-art non-volatile in-memory computing approaches, it reduces area by 42% and energy consumption by 37%, delivering simultaneous improvements in accuracy, compactness, and energy efficiency.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Natural Language Processing: Learning & Optimization for NLP

Application Category

• Search and Retrieval-Augmented AI: Vertical and domain-specific search
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications

Abstract

Hyperdimensional (HD) computing involves encoding of baseline information into large hypervectors and repeated Boolean operations to generate the output class hypervectors which are stored in an associative memory. The classification task is then performed through similarity search operation. While prior studies have focused mostly on accelerating HD search operation using TCAMs based on emerging non-volatile memories, considering the dominant contribution of the encoder module to the energy and latency landscape specifically for complex datasets such as language recognition, DNA sequencing, etc., in this work, we propose energy- and area-efficient single FDSOI ferroelectric (Fe)FET-based logic-in-memory implementations of XOR and 3-input majority gates for N-gram HD encoders. We utilize the proposed FeFET-based encoder in a HD spam filtering accelerator and show that it outperforms the prior emerging non-volatile memory-based implementations in terms of area and energy-efficiency while exhibiting a high classification accuracy of 91.38% on the SMS Spam Collection dataset.

Problem

• Design energy-efficient FeFET-based encoder for hyperdimensional computing.
• Accelerate N-gram encoding in complex tasks like spam filtering.
• Improve area and energy efficiency over prior non-volatile memory implementations.

Innovation

• FeFET-based logic-in-memory encoder design
• Energy- and area-efficient XOR and majority gates
• HD spam filtering accelerator with high accuracy