🤖 AI Summary
This work addresses the impact of device variability—specifically in timing, coupling strength, and bias offset—on the performance of simulated annealing in physical p-bit hardware by introducing the first open-source, GPU-accelerated framework capable of modeling such non-idealities. Leveraging CUDA for efficient large-scale simulation, the study reveals, for the first time, that timing variability can enhance rather than degrade algorithmic performance. Validated on the MAX-CUT benchmark, the framework achieves up to two orders of magnitude speedup over CPU-based implementations across problem sizes ranging from 800 to 20,000 nodes, demonstrating both the efficacy of incorporating realistic device variations and the scalability of the proposed platform.
📝 Abstract
Probabilistic computing using probabilistic bits (p-bits) presents an efficient alternative to traditional CMOS logic for complex problem-solving, including simulated annealing and machine learning. Realizing p-bits with emerging devices such as magnetic tunnel junctions introduces device variability, which was expected to negatively impact computational performance. However, this study reveals an unexpected finding: device variability can not only degrade but also enhance algorithm performance, particularly by leveraging timing variability. This paper introduces a GPU-accelerated, open-source simulated annealing framework based on p-bits that models key device variability factors-timing, intensity, and offset-to reflect real-world device behavior. Through CUDA-based simulations, our approach achieves a two-order magnitude speedup over CPU implementations on the MAX-CUT benchmark with problem sizes ranging from 800 to 20,000 nodes. By providing a scalable and accessible tool, this framework aims to advance research in probabilistic computing, enabling optimization applications in diverse fields.