Surrogate Neural Architecture Codesign Package (SNAC-Pack)

2025-12-17

AI Summary

Existing neural architecture search (NAS) methods struggle to jointly optimize accuracy, resource utilization, and inference latency for FPGA deployment, often relying on mismatched proxy metrics (e.g., BOPs) and requiring costly per-model synthesis. This work introduces the first hardware-aware co-design framework tailored for FPGA deployment, integrating NAS with lightweight, analytical FPGA resource and latency proxy models to enable synthesis-free, end-to-end multi-objective Bayesian optimization. By bypassing traditional synthesis bottlenecks, our approach achieves 63.84% accuracy on a high-energy physics jet classification task. On a Virtex UltraScale+ FPGA, it matches baseline accuracy while attaining resource consumption and BOPs comparable to optimized baselines. The framework significantly improves the efficiency and practicality of hardware-algorithm co-design, enabling rapid, accurate, and resource-aware neural architecture exploration without iterative synthesis.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Learning to Search
• Cognitive Modeling & Cognitive Systems: Agent Architectures

Application Category

• Responsible Web: Human-perceived consequences of algorithmic deployment on the web
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• User Modeling, Personalization and Recommendation: Fairness-aware retrieval and ranking

Abstract

Neural Architecture Search is a powerful approach for automating model design, but existing methods struggle to accurately optimize for real hardware performance, often relying on proxy metrics such as bit operations. We present Surrogate Neural Architecture Codesign Package (SNAC-Pack), an integrated framework that automates the discovery and optimization of neural networks focusing on FPGA deployment. SNAC-Pack combines Neural Architecture Codesign's multi-stage search capabilities with the Resource Utilization and Latency Estimator, enabling multi-objective optimization across accuracy, FPGA resource utilization, and latency without requiring time-intensive synthesis for each candidate model. We demonstrate SNAC-Pack on a high energy physics jet classification task, achieving 63.84% accuracy with resource estimation. When synthesized on a Xilinx Virtex UltraScale+ VU13P FPGA, the SNAC-Pack model matches baseline accuracy while maintaining comparable resource utilization to models optimized using traditional BOPs metrics. This work demonstrates the potential of hardware-aware neural architecture search for resource-constrained deployments and provides an open-source framework for automating the design of efficient FPGA-accelerated models.

Problem

• Optimizes neural networks for FPGA deployment with hardware-aware metrics.
• Automates multi-objective optimization of accuracy, resource use, and latency.
• Eliminates need for time-intensive synthesis in architecture search.

Innovation

• Automates neural network discovery for FPGA deployment
• Combines multi-stage search with hardware resource estimation
• Enables multi-objective optimization without synthesis for each candidate