🤖 AI Summary
To address the low compilation efficiency, excessive circuit depth, and high qubit-routing overhead in variational quantum algorithms (VQAs) for Hamiltonian simulation on NISQ devices, this work proposes the first global compilation framework based on a Pauli-exponential intermediate representation (IR). Innovatively, IR synthesis is formulated as a binary symplectic form (BSF) column-weight minimization problem; we design a heuristic BSF simplification algorithm and a Tetris-inspired gate scheduling strategy to jointly optimize Clifford transformations, Pauli gate merging, and qubit routing. Evaluated across diverse VQAs, instruction set architectures, and hardware topologies, our method significantly outperforms state-of-the-art compilers: it reduces average circuit depth by 28.6%, decreases two-qubit gate count by 34.1%, and improves execution fidelity by 4.7 percentage points.
📝 Abstract
Variational quantum algorithms (VQA) based on Hamiltonian simulation represent a specialized class of quantum programs well-suited for near-term quantum computing applications due to its modest resource requirements in terms of qubits and circuit depth. Unlike the conventional single-qubit (1Q) and two-qubit (2Q) gate sequence representation, Hamiltonian simulation programs are essentially composed of disciplined subroutines known as Pauli exponentiations (Pauli strings with coefficients) that are variably arranged. To capitalize on these distinct program features, this study introduces PHOENIX, a highly effective compilation framework that primarily operates at the high-level Pauli-based intermediate representation (IR) for generic Hamiltonian simulation programs. PHOENIX exploits global program optimization opportunities to the greatest extent, compared to existing SOTA methods despite some of them also utilizing similar IRs. PHOENIX employs the binary symplectic form (BSF) to formally describe Pauli strings and reformulates IR synthesis as reducing the column weights of BSF by appropriate Clifford transformations. It comes with a heuristic BSF simplification algorithm that searches for the most appropriate 2Q Clifford operators in sequence to maximally simplify the BSF at each step, until the BSF can be directly synthesized by basic 1Q and 2Q gates. PHOENIX further performs a global ordering strategy in a Tetris-like fashion for these simplified IR groups, carefully balancing optimization opportunities for gate cancellation, minimizing circuit depth, and managing qubit routing overhead. Experimental results demonstrate that PHOENIX outperforms SOTA VQA compilers across diverse program categories, backend ISAs, and hardware topologies.