Parallel tempering–inspired distributed binary optimization with in-memory computing
🤖 AI Summary
To address the low hardware efficiency and weak search capability of conventional algorithms for binary optimization—particularly Boolean satisfiability (SAT) solving—this paper proposes PTIC-WalkSAT, the first parallel tempering (PT)-based co-design framework tailored for in-memory computing (IMC) architectures. Methodologically, it pioneers the adaptation of physics-inspired parallel tempering to IMC hardware, enhancing global search through inter-replica communication and tightly integrating it with the WalkSAT heuristic to achieve algorithm-hardware co-optimization. Its key contributions are: (i) high flexibility with minimal overhead, enabling seamless compatibility with diverse IMC-based SAT solvers; and (ii) significant performance gains—on standard SAT benchmarks, PTIC-WalkSAT reduces iteration counts for 84.0% of instances compared to baseline WalkSAT and consumes only 1% of the accelerator’s total energy, thereby substantially improving both energy efficiency and solution quality.
Application Category
📝 Abstract
In-memory computing (IMC) has been shown to be a promising approach for solving binary optimization problems while significantly reducing energy and latency. Building on the advantages of parallel computation, we propose an IMC-compatible parallelism framework based on the physics-inspired parallel tempering (PT) algorithm, enabling cross-replica communication to improve the performance of IMC solvers. This framework enables an IMC solver not only to improve performance beyond what can be achieved through parallelization, but also affords greater flexibility for the search process with low hardware overhead. We justify that the framework can be applied to almost any IMC solver. We demonstrate the effectiveness of the framework for the Boolean satisfiability (SAT) problem, using the WalkSAT heuristic as a proxy for existing IMC solvers. The resulting PT-inspired cooperative WalkSAT (PTIC-WalkSAT) algorithm outperforms the standard WalkSAT heuristic in terms of the iterations-to-solution in 84.0% of the tested problem instances and its na""ive parallel variant (PA-WalkSAT) does so in 64.9% of the instances, and with a higher success rate in the majority of instances. An estimate of the energy overhead of the PTIC framework for two hardware accelerator architectures indicates that in both cases the overhead of running the PTIC framework would be less than 1% of the total energy required to run each accelerator.
Problem
Research questions and friction points this paper is trying to address.
Enhancing IMC solvers via parallel tempering-inspired framework
Improving binary optimization performance with cross-replica communication
Reducing energy overhead in hardware accelerators for SAT problems
Innovation
Methods, ideas, or system contributions that make the work stand out.
In-memory computing for binary optimization
Parallel tempering-inspired distributed framework
Cross-replica communication enhances solver performance
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