Scalable IP Mimicry: End-to-End Deceptive IP Blending to Overcome Rectification and Scale Limitations of IP Camouflage

2025-12-12

AI Summary

Semiconductor IP piracy incurs annual losses of $22.5–60 billion; existing IP obfuscation techniques suffer from high post-synthesis correction overhead, poor scalability, and incompatibility between And-Inverter Graph (AIG) representations and reverse-engineering (RE) workflows. Method: We propose an end-to-end scalable IP obfuscation paradigm: (1) full-module-level biomimetic deception—replacing gate-level hiding to fundamentally thwart RE; (2) a novel graph-matching algorithm resolving the logical representation mismatch between AIG and RE analysis; (3) DNAS-driven NAND-array modeling for efficient, scalable obfuscation; and (4) a biomimetic-aware partitioning strategy enabling industrial-scale designs. Results: Our approach eliminates post-generation correction overhead entirely, demonstrates strong robustness against SAT- and GNN-based RE attacks, and significantly enhances the practicality, scalability, and security of IP obfuscation.

Technology Category

• Search and Optimization: Distributed Search
• Machine Learning: Hardware-aware ML
• Knowledge Representation and Reasoning: Computational Complexity of Reasoning

Application Category

• Graph Algorithms and Modeling for the Web: Representation, reconstruction, and subgraph or motif discovery in Web-related graphs
• Security and Privacy: Large-scale security measurements
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs

Abstract

Semiconductor intellectual property (IP) theft incurs estimated annual losses ranging from $225 billion to $600 billion. Despite initiatives like the CHIPS Act, many semiconductor designs remain vulnerable to reverse engineering (RE). IP Camouflage is a recent breakthrough that expands beyond the logic gate hiding of traditional camouflage through "mimetic deception," where an entire module masquerades as a different IP. However, it faces key limitations: requires a high-overhead post-generation rectification step, is not easily scalable, and uses an AIG logic representation that is mismatched with standard RE analysis flows. This paper addresses these shortcommings by introducing two novel, end-to-end models. We propose a Graph-Matching algorithm to solve the representation problem and a DNAS-based NAND Array model to achieve scalability. To facilitate this, we also introduce a mimicry-aware partitioning method, enabling a divide-and-conquer approach for large-scale designs. Our results demonstrate that these models are resilient to SAT and GNN-RE attacks, providing efficient and scalable paths for end-to-end deceptive IP design.

Problem

• Overcomes scalability and rectification limitations in IP camouflage
• Introduces end-to-end models for deceptive IP design against reverse engineering
• Provides resilience to SAT and GNN-RE attacks in semiconductor IP protection

Innovation

• Graph-Matching algorithm solves representation mismatch
• DNAS-based NAND Array model achieves scalability
• Mimicry-aware partitioning enables divide-and-conquer approach