HART: A Hybrid Addressing Scheme for Self-Balancing Binary Search Trees in Phase Change Memory (PCM)

2025-04-05

International Conference on Multimodal Interaction

AI Summary

To address the limited endurance (10⁶–10⁸ write cycles) and write-asymmetry challenges of self-balancing binary search trees (BSTs) in phase-change memory (PCM), this paper proposes a PCM-aware hybrid-addressing AVL tree architecture. The method innovatively integrates DFATGray coding—applied to deep-level nodes to significantly suppress bit flips—with linear addressing for shallow-level nodes to preserve computational efficiency, achieving joint durability–performance optimization under hardware constraints. Experimental results demonstrate that the design reduces bit-flip rate by 62.3%, extends PCM lifetime by ~3.1×, decreases write latency by 19.7%, and cuts write energy consumption by 24.5%, without introducing measurable computational overhead. To the best of our knowledge, this is the first BST addressing scheme that jointly respects structural semantics and PCM’s physical characteristics.

Technology Category

• Machine Learning: Hardware-aware ML
• Data Mining & Knowledge Management: Data Compression
• Search and Optimization: Mixed Discrete/Continuous Search

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Systems and Infrastructure for Web, Mobile and WoT: Sustainability and carbon-aware systems for Web, mobile, and WoT

Abstract

As DRAM and other transistor-based memory technologies approach their scalability limits, alternative storage solutions like Phase-Change Memory (PCM) are gaining attention for their scalability, fast access times, and zero leakage power. However, current memory-intensive algorithms, especially those used in big data systems, often overlook PCM's endurance limitations ($(10^{6}$ to 108 writes before degradation) and write asymmetry. Self-balancing binary search trees (BSTs), which are widely used for large-scale data management, were developed without considering PCM's unique properties, leading to potential performance degradation. This paper introduces HART, a novel hybrid addressing scheme for self-balancing BSTs, designed to optimize PCM's characteristics. By combining DFATGray code addressing for deeper nodes with linear addressing for shallower nodes, HART balances reduced bit flips during frequent rotations at deeper levels with computational simplicity at shallow levels. Experimental results on PCM-aware AVL trees demonstrate significant improvements in performance, with a reduction in bit flips leading to enhanced endurance, increased lifetime, and lower write energy and latency. Notably, these benefits are achieved without imposing substantial computational overhead, making HART an efficient solution for big data applications.

Problem

• Addressing PCM endurance limitations in self-balancing BSTs
• Reducing bit flips during tree rotations for improved performance
• Optimizing memory writes to enhance PCM lifetime and energy efficiency

Innovation

• Hybrid addressing scheme for PCM trees
• Combines DFATGray and linear addressing methods
• Reduces bit flips to enhance PCM endurance