Evaluating Architectural Trade-offs in CGRAs: The Impact of Scratchpad Memory and Heterogeneity on Compute-Intensive Kernels

2026-06-25

AI Summary

This study systematically evaluates the impact of processing element heterogeneity and on-chip scratchpad memory (SPM) in coarse-grained reconfigurable architectures (CGRAs) for high-throughput streaming workloads under power and area constraints in edge computing, with a focus on Vision Transformers. Experimental results demonstrate that SPM reduces memory traffic by up to 8×. Homogeneous CGRAs achieve up to 5× acceleration for matrix computations while exhibiting 4.4–8.2× lower area overhead compared to existing CGRA designs. In contrast, heterogeneous CGRAs deliver superior energy efficiency for data-reordering-intensive tasks. This work provides design guidelines and selection criteria for CGRAs targeting edge applications that must balance arithmetic intensity with stringent resource constraints.

Abstract

Modern edge computing applications, particularly high-throughput stream processing like Vision Transformers (ViTs), demand massive spatial parallelism and efficient data movement under tight power and area constraints. Coarse-Grained Reconfigurable Architectures (CGRAs) offer a promising paradigm to balance performance, flexibility, and energy efficiency. This paper analyzes the impact of two critical CGRA design choices: processing element heterogeneity and local data reuse support. We evaluate essential computational kernels (Fast Fourier Transform (FFT) and General Matrix Multiply (GEMM)) alongside an end-to-end seizure detection transformer workload across two distinct configurations: a baseline homogeneous architecture and a heterogeneous evolution integrating specialized functional units with an Scratchpad Memory (SPM). Our evaluation demonstrates that the SPM significantly optimizes data movement, reducing memory traffic eightfold compared to a memory-less design. While the heterogeneous architecture achieves superior energy efficiency for data-shuffling tasks, the homogeneous design minimizes area overhead by 4.4x to 8.2x relative to state-of-the-art CGRAs. Furthermore, it sustains a 700 MHz operating frequency, enabling up to a 5x execution speedup over the heterogeneous configuration during matrix computations. Ultimately, this work provides an architectural roadmap for selecting CGRA fabrics based on the arithmetic intensity, performance goals, and resource envelopes of edge-scale workloads.

Problem

• CGRAs
• scratchpad memory
• heterogeneity
• compute-intensive kernels
• edge computing

Innovation

• Coarse-Grained Reconfigurable Architecture
• Scratchpad Memory
• Processing Element Heterogeneity
• Data Movement Optimization
• Edge Computing