VeBPF Many-Core Architecture for Network Functions in FPGA-based SmartNICs and IoT

2025-12-14

AI Summary

Existing FPGA-based solutions lack highly configurable, multi-core architectures optimized for network packet processing. This paper proposes VeBPF—the first eBPF instruction set architecture (ISA)-compatible Verilog soft core—enabling a scalable, hardware-accelerated multi-core architecture that supports dynamic loading and parallel execution of eBPF programs. The architecture features fully parameterized core count scaling, runtime hot updates of packet-processing rules (<1 μs latency), and deployment without FPGA reconfiguration, while uniformly supporting resource-constrained IoT devices and high-end FPGA-based smart NICs. Evaluated on Xilinx and Intel FPGAs, it achieves scalable parallelism across dozens of cores. A comprehensive open-source toolchain—including a Cocotb/Python-based automated test framework and a control software library—is provided alongside the RTL source code. The core contribution is the first deep hardware implementation of the eBPF ISA, uniquely balancing programmability, ultra-low latency, and cross-platform portability.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Agent Architectures
• Computer Vision: Learning & Optimization for CV

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Security and Privacy: Large-scale security measurements

Abstract

FPGA-based SmartNICs and IoT devices integrating soft-processors for network function execution have emerged to address the limited hardware reconfigurability of DPUs and MCUs. However, existing FPGA-based solutions lack a highly configurable many-core architecture specialized for network packet processing. This work presents VeBPF many-core architecture, a resource-optimized and highly configurable many-core architecture composed of custom VeBPF (Verilog eBPF) CPU cores designed for FPGA-based packet processing. The VeBPF cores are eBPF ISA compliant and implemented in Verilog HDL for seamless integration with existing FPGA IP blocks and subsystems. The proposed many-core architecture enables parallel execution of multiple eBPF rules across multiple VeBPF cores, achieving low-latency packet processing. The architecture is fully parameterizable, allowing the number of VeBPF cores and eBPF rules to scale according to application requirements and available FPGA resources. eBPF rules can be dynamically updated at run time without requiring FPGA reconfiguration, enabling flexible and adaptive network processing. The design incorporates hardware and computer architecture optimizations that support deployment across a wide range of platforms, from low-end FPGA-based IoT devices to high-end FPGA-based SmartNICs. In addition, we present automated testing and simulation frameworks developed using open-source tools such as Python and Cocotb. The VeBPF cores, many-core architecture, control software libraries, and simulation infrastructure are released as open source to support further research in FPGA-based many-core systems, eBPF acceleration, SmartNICs, IoT, and network security.

Problem

• Designs a configurable many-core architecture for FPGA-based network packet processing
• Enables parallel execution of eBPF rules across multiple cores for low latency
• Supports dynamic eBPF rule updates without FPGA reconfiguration for flexibility

Innovation

• VeBPF many-core architecture for FPGA packet processing
• Parameterizable design scales cores and rules dynamically
• Run-time eBPF rule updates without FPGA reconfiguration