DAPO: Design Structure-Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learning

2025-12-12

AI Summary

Existing high-level synthesis (HLS) tools employ fixed optimization pass orders, which fail to adapt to the heterogeneous design semantics of FPGA accelerators, thereby limiting hardware performance. To address this, we propose a structure-aware adaptive pass ordering framework: first, parsing control- and data-flow graphs to model design semantics; second, applying graph contrastive learning to generate structural-aware graph embeddings; third, integrating a lightweight hardware parser to accurately predict timing, area, and power; and finally, employing deep deterministic policy gradient (DDPG)-based reinforcement learning to dynamically search for optimal pass sequences. This work is the first to synergistically combine graph contrastive learning with reinforcement learning for HLS pass ordering, overcoming the limitations of static rule-based and black-box search approaches. Evaluated on canonical benchmarks, our method achieves an average speedup of 2.36× over Vitis HLS and significantly improves PPA (performance, power, area) co-optimization.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Learning to Search
• Computer Vision: Learning & Optimization for CV

Application Category

• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs

Abstract

High-Level Synthesis (HLS) tools are widely adopted in FPGA-based domain-specific accelerator design. However, existing tools rely on fixed optimization strategies inherited from software compilations, limiting their effectiveness. Tailoring optimization strategies to specific designs requires deep semantic understanding, accurate hardware metric estimation, and advanced search algorithms -- capabilities that current approaches lack. We propose DAPO, a design structure-aware pass ordering framework that extracts program semantics from control and data flow graphs, employs contrastive learning to generate rich embeddings, and leverages an analytical model for accurate hardware metric estimation. These components jointly guide a reinforcement learning agent to discover design-specific optimization strategies. Evaluations on classic HLS designs demonstrate that our end-to-end flow delivers a 2.36 speedup over Vitis HLS on average.

Problem

• Optimizes FPGA accelerator design with tailored strategies
• Extracts program semantics using graph contrastive learning
• Improves hardware performance via reinforcement learning search

Innovation

• Graph contrastive learning extracts program semantics
• Analytical model estimates hardware metrics accurately
• Reinforcement learning discovers design-specific optimization strategies