Versatile silicon integrated photonic processor: a reconfigurable solution for netx-generation AI clusters

2025-04-02

AI Summary

To address the escalating computational demands and bandwidth bottlenecks confronting electronic circuits in AI clusters—and the limitations of existing silicon photonic chips, including functional inflexibility and insufficient hardware–software co-design—this project develops the world’s first reconfigurable silicon photonic processor. The chip integrates 40 programmable photonic units and over 160 photonic devices, enabling, for the first time on a single die, unified support for AI acceleration, signal processing, optical switching, and physical unclonable function (PUF)-based encryption. We propose a detectorless, automated compilation–testing–feedback optimization framework that supports both bidirectional unitary and unidirectional non-unitary matrix operations, microring wavelength locking, and photonic PUF. Experimental validation demonstrates 4×4 bidirectional/unidirectional matrix multiplication, inference of image recognition networks, and 4×4 optical switching—achieving reduced system latency and enhanced bandwidth while maintaining full CMOS process compatibility.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Computational Photography, Image & Video Synthesis
• Search and Optimization: Algorithm Configuration

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Economics, Online Markets and Human Computation: Economic ramifications for generative AI infrastructure and applications
• Security and Privacy: Security and privacy of machine learning and AI applications

Abstract

The Artificial Intelligence models pose serious challenges in intensive computing and high-bandwidth communication for conventional electronic circuit-based computing clusters. Silicon photonic technologies, owing to their high speed, low latency, large bandwidth, and complementary metal-oxide-semiconductor compatibility, have been widely implemented for data transfer and actively explored as photonic neural networks in AI clusters. However, current silicon photonic integrated chips lack adaptability for multifuncional use and hardware-software systematic coordination. Here, we develop a reconfigurable silicon photonic processor with $40$ programmable unit cells integrating over $160$ component, which, to the best of our knowledge, is the first to realize diverse functions with a chip for AI clusters, from computing acceleration and signal processing to network swtiching and secure encryption. Through a self-developed automated testing, compilation, and tuning framework to the processor without in-network monitoring photodetectors, we implement $4 imes4$ dual-direction unitary and $3 imes3$ uni-direction non-unitary matrix multiplications, neural networks for image recognition, micro-ring modulator wavelength locking, $4 imes4$ photonic channel switching , and silicon photonic physical unclonable functions. This optoelectronic processing system, incorporating the photonic processor and its software stack, paves the way for both advanced photonic system-on-chip design and the construction of photo-electronic AI clusters.

Problem

• Addresses high computing and communication demands in AI clusters
• Overcomes lack of adaptability in current silicon photonic chips
• Integrates diverse functions like computing and encryption on one chip

Innovation

• Reconfigurable silicon photonic processor
• Automated testing and tuning framework
• Diverse functions for AI clusters