Problem
Research questions and friction points this paper is trying to address.
hybrid quantum-classical systems
system topology
resource contention
QPU scalability
controller bottlenecks
HybridQC: Hardware-Grounded Simulation of Tightly Integrated Hybrid Quantum-Classical Systems
🤖 AI Summary
This work addresses the limitations of existing hybrid quantum-classical systems, which are constrained by classical control, communication, and scheduling bottlenecks, and notes that conventional simulators struggle to evaluate performance at the topological level. To overcome these challenges, the authors propose the first end-to-end, topology-aware discrete-event simulator capable of supporting both quantum annealing and digital quantum computing devices. The simulator models task phases using directed acyclic graphs, incorporates interchangeable scheduling policies, and is calibrated against real hardware data from D-Wave and IBM devices. Experimental results demonstrate average absolute percentage errors of 3.92%–8.04% on quantum annealers and 5.26%–19.01% on gate-based platforms, effectively revealing the critical impact of system scalability and scheduling strategies on task completion time.
📝 Abstract
Hybrid quantum-classical application performance is increasingly limited by classical control, host-to-QPU communication, and scheduling rather than quantum execution. Existing simulators and runtime interfaces analyze individual kernels but fail to address system-topology questions, such as controller bottlenecks, diminishing returns of QPU capacity, or resource contention under heterogeneous workloads. We introduce HybridQC, a topology-aware discrete-event simulator for tightly coupled hybrid compute units (HCUs). HybridQC models HCUs as configurable graphs of classical processors, memory, controllers, quantum annealing (QA) and digital quantum computing (DQC) devices, and communication links. It decomposes jobs into typed, directed acyclic graphs of stages, ranging from input preparation to classical postprocessing, executed under interchangeable scheduling policies. Calibrated with live measurements from D-Wave (Advantage 1 and 2) and IBM (Kingston, Marrakesh, and Fez) processors, HybridQC distinguishes physical QPU occupancy from cloud wall-clock latency. The models achieve mean absolute percentage errors of 3.92%-8.04% for D-Wave QPU access time and 5.26%-19.01% for IBM quantum-seconds measurements. Workload experiments reveal that a balanced 10x HCU scaling improves makespan by only 2.19x-3.42x, while altering scheduling policies shifts makespan by up to 1.80x for a 20-job workload. Scalability varies heavily by workload dimension: a 100x input data increase yields a 306 s median runtime, whereas a 100x joint increase in circuit count, shot count, and circuit depth drives runtime to 4.806x10^7 s on an unchanged HCU. HybridQC offers a systematic framework for evaluating the topology, scheduling, and scaling limits of hybrid architectures prior to physical deployment.
Innovation
Methods, ideas, or system contributions that make the work stand out.
Hybrid quantum-classical simulation
Topology-aware modeling
Discrete-event simulation
Heterogeneous workload scheduling
QPU-system co-design
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