ARM MTE Performance in Practice (Extended Version)

2026-01-16

AI Summary

This study addresses the lack of systematic evaluation of ARM Memory Tagging Extension (MTE) performance under real hardware and diverse workloads, particularly across different microarchitectures and security use cases. For the first time, we comprehensively quantify MTE’s performance overhead on multiple ARM processors—including Google Pixel 8/9, AmpereOne, and Apple M5—using a mix of general-purpose and server workloads such as SPEC CPU, RocksDB, and Nginx. We further analyze MTE’s applicability in memory safety, sandboxing, and control-flow integrity mechanisms. Through real-platform profiling and microarchitectural bottleneck analysis, we identify the root causes of slowdowns up to 6.64×, correct methodological flaws in prior studies, and delineate MTE’s practical boundaries: overhead is generally manageable in most scenarios, certain workloads demand hardware-level optimizations, and several security applications are already deployment-ready.

Technology Category

• Machine Learning: Hardware-aware ML
• Application Domains: Security
• Multiagent Systems: Mechanism Design

Application Category

• Security and Privacy: Large-scale security measurements
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics

Abstract

We present the first comprehensive analysis of ARM MTE hardware performance on four different microarchitectures: ARM Big (A7x), Little (A5x), and Performance (Cortex-X) cores on the Google Pixel 8 and Pixel 9, and on Ampere Computing's AmpereOne CPU core. We also include preliminary analysis of MTE on Apple's M5 chip. We investigate performance in MTE's primary application -- probabilistic memory safety -- on both SPEC CPU benchmarks and in server workloads such as RocksDB, Nginx, PostgreSQL, and Memcached. While MTE often exhibits modest overheads, we also see performance slowdowns up to 6.64x on certain benchmarks. We identify the microarchitectural cause of these overheads and where they can be addressed in future processors. We then analyze MTE's performance for more specialized security applications such as memory tracing, time-of-check time-of-use prevention, sandboxing, and CFI. In some of these cases, MTE offers significant advantages today, while the benefits for other cases are negligible or will depend on future hardware. Finally, we explore where prior work characterizing MTE performance has either been incomplete or incorrect due to methodological or experimental errors.

Problem

• ARM MTE
• performance overhead
• memory safety
• microarchitectures
• security applications

Innovation

• ARM MTE
• memory safety
• microarchitectural performance
• security applications
• hardware evaluation