Pinball: A Cryogenic Predecoder for Quantum Error Correction Decoding Under Circuit-Level Noise

2025-12-10

AI Summary

To address bottlenecks—including low decoding accuracy, high power consumption, and severe bandwidth pressure—of cryogenic pre-decoders for million-qubit fault-tolerant quantum computers operating at 4 K, this work presents the first cryo-CMOS pre-decoder co-designed with circuit-level noise modeling. Innovatively implemented in 22 nm fully-depleted silicon-on-insulator (FDSOI) technology with 4 K experimental validation, it features full-path error propagation modeling integrated with synergistic voltage/frequency scaling and body-bias optimization to realize a lightweight architecture. Compared to state-of-the-art cryogenic and room-temperature solutions, it reduces logical error rates by 32.6× and 5×, respectively—achieving nearly six orders-of-magnitude improvement; compresses syndrome bandwidth by 3780×; cuts power consumption by 22.2×; and improves energy efficiency by 67.4×. Within a stringent 1.5 W cooling budget at 4 K, it supports 2,668 distance-21 logical qubits.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding

Application Category

• Security and Privacy: Applications of cryptography
• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments
• Economics, Online Markets and Human Computation: Economic aspects of blockchain and cryptocurrencies

Abstract

Scaling fault tolerant quantum computers, especially cryogenic systems, to millions of qubits is challenging due to poorly-scaling data processing and power consumption overheads. One key challenge is the design of decoders for real-time quantum error correction (QEC), which demands high data rates for error processing; this is particularly apparent in systems with cryogenic qubits and room temperature (RT) decoders. In response, cryogenic predecoding using lightweight logic has been proposed to handle common, sparse errors in the cryogenic domain. However, prior work only accounts for a subset of error sources present in real-world quantum systems with limited accuracy, often degrading performance below a useful level in practical scenarios. Furthermore, prior reliance on SFQ logic precludes detailed architecture-technology co-optimization. To address these shortcomings, this paper introduces Pinball, a comprehensive design in cryogenic CMOS of a QEC predecoder tailored to realistic, circuit-level noise. By accounting for error generation and propagation through QEC circuits, our design achieves higher predecoding accuracy, outperforming logical error rates (LER) of the current state-of-the-art cryogenic predecoder by nearly six orders of magnitude. Remarkably, despite operating under much stricter power and area constraints, Pinball also reduces LER by 32.58x and 5x, respectively, compared to the state-of-the-art RT predecoder and RT ensemble configurations. By increasing cryogenic coverage, we also reduce syndrome bandwidth up to 3780.72x. Through co-design with 4 K-characterized 22 nm FDSOI technology, we achieve a peak power consumption under 0.56 mW. Voltage/frequency scaling and body biasing enable 22.2x lower typical power consumption, yielding up to 67.4x total energy savings. Assuming a 4 K power budget of 1.5 W, our predecoder supports up to 2,668 logical qubits at d=21.

Problem

• Designs a cryogenic predecoder for quantum error correction under circuit-level noise.
• Addresses high data rate demands and power consumption in fault-tolerant quantum computers.
• Improves accuracy and reduces logical error rates compared to existing predecoders.

Innovation

• Cryogenic CMOS predecoder for quantum error correction
• Co-design with 22 nm FDSOI technology for low power
• Reduces syndrome bandwidth and improves error rate accuracy