FastLEC: Parallel Datapath Equivalence Checking with Hybrid Engines

2025-12-06

AI Summary

Combinational equivalence checking (CEC) for datapath circuits remains challenged by complex arithmetic structures and the limited scalability of individual formal verification techniques—SAT, BDD, or exact simulation. This paper proposes a parallel CEC framework that synergistically integrates SAT solving, BDD-based reasoning, and exact simulation. Key innovations include a regression-guided engine scheduling strategy, a datapath-aware dynamic divide-and-conquer mechanism, and a reference-counting–based memory optimization coupled with a GPU-accelerated backend. Evaluated on 368 benchmark circuits, the framework verifies 5.07× more circuits than ABC’s &cec under 32-core execution, achieving 2.67–3.33× speedup in PAR-2 runtime. With GPU acceleration enabled, end-to-end performance improves by an additional 4.07×. The approach significantly advances the efficiency and scalability of datapath CEC, enabling robust verification of large, arithmetic-intensive designs.

Technology Category

• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Search and Optimization: Sampling/Simulation-based Search
• Knowledge Representation and Reasoning: Computational Complexity of Reasoning

Application Category

• Security and Privacy: Large-scale security measurements
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs

Abstract

Combinational equivalence checking (CEC) remains a challenge EDA task in the formal verification of datapath circuits due to their complex arithmetic structures and the limited capability or scalability of SAT, BDD, and exact-simulation (ES) based techniques when used independently. This work presents FastLEC, a hybrid prover that unifies these three formal reasoning engines and introduces three strategies that substantially enhance verification efficiency. First, a regression-based engine-scheduling heuristic predicts solver effectiveness, enabling more accurate and balanced allocation of computational resources. Second, datapath-structure-aware partitioning strategies, along with a dynamic divide-and-conquer SAT prover, exploit the regularity of arithmetic designs while preserving completeness. Third, the memory overhead of ES is significantly reduced through address-reference-count tracking, and simulation is further accelerated through a GPU-enabled backend. FastLEC is evaluated across 368 datapath circuits. Using 32 CPU cores, it proves 5.07x more circuits than the widely used ABC &cec tool. Compared with the latest best datapath-oriented serial and parallel CEC provers, FastLEC outperforms them by 3.33x and 2.67x in PAR-2 time, demonstrating an improvement of 74 newly solved circuits. With the addition of a single GPU, it achieves a further 4.07x improvement. The prover also demonstrates excellent scalability.

Problem

• Enhances equivalence checking for complex arithmetic datapath circuits
• Improves verification efficiency through hybrid engines and smart scheduling
• Reduces memory overhead and accelerates simulation with GPU integration

Innovation

• Hybrid prover unifies SAT, BDD, and exact-simulation engines.
• Dynamic divide-and-conquer SAT prover exploits arithmetic design regularity.
• GPU acceleration and memory optimization boost simulation performance.