A Novel FeFET Differential Bit-Cell With Hybrid Volatile and Non-Volatile Memory Modes

2026-06-18

AI Summary

This work addresses the limitations of conventional non-volatile SRAM (nvSRAM), which suffers from large cell area due to embedded non-volatile memory (eNVM) integration, explicit backup/restore operations, high leakage in CMOS SRAM, and long eNVM write latency. To overcome these challenges, the authors propose a four-transistor (4T) differential memory cell composed of two cross-coupled ferroelectric field-effect transistors (FeFETs) and two access transistors. This design realizes, for the first time, a hybrid-mode nvSRAM that seamlessly switches between volatile and non-volatile operation without requiring explicit backup or restore. Compared to both 6T SRAM and existing nvSRAM architectures, the proposed cell offers a smaller footprint and potential cross-coupling gain. In non-volatile mode, it achieves an ultra-low static power consumption of 0.13 μW and a write latency of merely 2 ns, significantly reducing energy, delay, and chip area overhead.

Abstract

Non-volatile SRAM (nvSRAM) designs have been investigated to address the high leakage power of CMOS-based SRAM and the large write latency of emerging non-volatile memory (eNVM) technologies. However, prior nvSRAM designs that combine SRAM with eNVM devices typically require backup and restore (B\&R) operations and incur significant cell-area overhead. Here, we propose a differential memory bit-cell consisting of a pair of cross-coupled ferroelectric field-effect transistors (FeFETs) and a pair of access transistors, resulting in a four-transistor (4T) structure, which is smaller than conventional 6T SRAM and many prior nvSRAM designs. The proposed bit-cell can be configured to operate in either volatile or non-volatile mode by adjusting the write conditions. In the non-volatile mode, the proposed nvSRAM achieves a store power of 0.13~$μ$W with a 2~ns store time, and no explicit B\&R operation is required. The proposed bit-cell can also be viewed as a cross-coupled gain cell, enabling further applications.

Problem

• nvSRAM
• backup and restore
• cell-area overhead
• non-volatile memory
• leakage power

Innovation

• FeFET
• nvSRAM
• differential bit-cell
• hybrid memory
• 4T architecture