When Forgetting Builds Reliability: LLM Unlearning for Reliable Hardware Code Generation

2025-12-04

AI Summary

Large language models (LLMs) exhibit reliability issues in hardware code generation due to memorization of proprietary IP, contamination of evaluation benchmarks, and adoption of unsafe coding patterns. Method: This paper proposes the first syntax-aware selective forgetting framework tailored for RTL code generation. It integrates a syntax-preserving forgetting strategy with a fine-grained, floorplan-aware selective loss function, enabling precise removal of harmful knowledge in a single training pass. Contribution/Results: Experiments demonstrate that our method supports forgetting sets three times larger than prior approaches while strictly preserving RTL syntactic correctness and functional equivalence—without degrading the model’s original code-generation capability. Crucially, this work is the first to explicitly incorporate hardware semantics—including synthesis constraints and module hierarchy—into the forgetting mechanism. By grounding forgetting in domain-specific hardware knowledge, it establishes a novel paradigm for trustworthy, AI-driven hardware design.

Technology Category

• Machine Learning: Hardware-aware ML
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Humans and AI: Human-Aware Planning and Behavior Prediction

Application Category

• Search and Retrieval-Augmented AI: Large language models for search
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs

Abstract

Large Language Models (LLMs) have shown strong potential in accelerating digital hardware design through automated code generation. Yet, ensuring their reliability remains a critical challenge, as existing LLMs trained on massive heterogeneous datasets often exhibit problematic memorization of proprietary intellectual property (IP), contaminated benchmarks, and unsafe coding patterns. To mitigate these risks, we propose a novel unlearning framework tailored for LLM-based hardware code generation. Our method combines (i) a syntax-preserving unlearning strategy that safeguards the structural integrity of hardware code during forgetting, and (ii) a fine-grained floor-aware selective loss that enables precise and efficient removal of problematic knowledge. This integration achieves effective unlearning without degrading LLM code generation capabilities. Extensive experiments show that our framework supports forget sets up to 3x larger, typically requiring only a single training epoch, while preserving both syntactic correctness and functional integrity of register-transfer level (RTL) codes. Our work paves an avenue towards reliable LLM-assisted hardware design.

Problem

• Ensuring LLM reliability in hardware code generation
• Mitigating memorization of problematic IP and unsafe patterns
• Achieving effective unlearning without degrading code generation capabilities

Innovation

• Syntax-preserving unlearning strategy for hardware code
• Fine-grained floor-aware selective loss for knowledge removal
• Effective unlearning without degrading code generation capabilities