A Spatial Array for Spectrally Agile Wireless Processing

2025-12-03

AI Summary

To address the growing demand for high-frequency, wideband, spectrum-agile, and dynamically interference-resilient wireless communications, existing hardware faces a fundamental trade-off between energy efficiency and reconfigurability. This paper proposes a customized spatial array architecture—designed as a general-purpose compute core—that jointly optimizes communication and sensing workloads via co-design of task mapping and microarchitecture. Implemented in 32 nm CMOS using high-level synthesis (HLS), the architecture achieves near-ASIC performance: latency, throughput, area, and power are all within close proximity to application-specific integrated circuits (ASICs), delivering >90% of ASIC efficiency across diverse wireless signal processing tasks. Its key contribution is the first experimental validation that a general-purpose systolic array—when synergistically co-optimized with task mapping and architectural customization—can simultaneously attain ASIC-level energy efficiency and full-scenario reconfigurability. This establishes a scalable, spectrum-agile hardware paradigm that bridges the efficiency–flexibility gap in next-generation wireless systems.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Agent Architectures
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Data management and stream processing for Web, mobile and wireless applications
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs

Abstract

Massive MIMO is a cornerstone of next-generation wireless communication, offering significant gains in capacity, reliability, and energy efficiency. However, to meet emerging demands such as high-frequency operation, wide bandwidths, co-existence, integrated sensing, and resilience to dynamic interference, future systems must exhibit both scalability and spectral agility. These requirements place increasing pressure on the underlying processing hardware to be both efficient and reconfigurable. This paper proposes a custom-designed spatial array architecture that serves as a reconfigurable, general-purpose core optimized for a class of wireless kernels that commonly arise in diverse communications and sensing tasks. The proposed spatial array is evaluated against specialized cores for each kernel using High-Level Synthesis (HLS). Both the reconfigurable and specialized designs are synthesized in a 32 nm process to assess latency, throughput, area, and power in realistic processes. The results identify conditions under which general-purpose systolic architectures can approach the efficiency of specialized cores, thereby paving the way toward more scalable and agile systems.

Problem

• Designs a spatial array for scalable, spectrally agile wireless processing
• Addresses efficiency and reconfigurability in future wireless communication systems
• Compares reconfigurable and specialized cores for wireless kernels via HLS

Innovation

• Custom spatial array for reconfigurable wireless processing
• Evaluated against specialized cores using HLS synthesis
• General-purpose systolic architectures approach specialized core efficiency