In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss

2025-12-03

AI Summary

Non-volatile memory (NVM) exposes sensitive data due to inherent data persistence, yet conventional AES encryption incurs prohibitive area and power overheads and suffers from low throughput. Method: This work proposes a single-transistor, in-situ XOR encryption cell based on ferroelectric field-effect transistors (FeFETs), the first to eliminate the traditional two-device requirement for XOR logic. By leveraging multi-level threshold voltage encoding, a single FeFET simultaneously realizes encryption and decryption—enabling one-cycle decryption, single-write operation, and multi-level cell (MLC) storage without compromising memory density. Contribution/Results: Evaluated on a 128×128 array, the design achieves up to 45.2× higher encryption/decryption throughput versus AES-based solutions and reduces average neural network inference latency by 95%. It thus delivers high security, high storage density, and ultra-low hardware overhead in a unified architecture.

Technology Category

• Machine Learning: Hardware-aware ML
• Natural Language Processing: Ethics — Bias, Fairness, Transparency & Privacy
• Computer Vision: Multi-modal Vision

Application Category

• Security and Privacy: Applications of cryptography
• Responsible Web: Data and user privacy-enhancing technologies for the Web
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs

Abstract

Non-volatile memories (NVMs) offer negligible leakage power consumption, high integration density, and data retention, but their non-volatility also raises the risk of data exposure. Conventional encryption techniques such as the Advanced Encryption Standard (AES) incur large area overheads and performance penalties, motivating lightweight XOR-based in-situ encryption schemes with low area and power requirements. This work proposes an ultra-dense single-transistor encrypted cell using ferroelectric FET (FeFET) devices, which, to our knowledge, is the first to eliminate the two-memory-devices-per-encrypted-cell requirement in XOR-based schemes, enabling encrypted memory arrays to maintain the same number of storage devices as unencrypted arrays. The key idea is an in-memory single-FeFET XOR scheme, where the ciphertext is encoded in the device threshold voltage and leverages the direction-dependent current flow of the FeFET for single-cycle decryption; eliminating complementary bit storage also removes the need for two write cycles, allowing faster encryption. We extend the approach to multi-level-cell (MLC) FeFETs to store multiple bits per transistor. We validate the proposed idea through both simulation and experimental evaluations. Our analysis on a 128x128-bit array shows 2x higher encryption/decryption throughput than prior FeFET work and 45.2x/14.12x improvement over AES, while application-level evaluations using neural-network benchmarks demonstrate average latency reductions of 50% and 95% compared to prior FeFET-based and AES-based schemes, respectively.

Problem

• Enables encrypted memory arrays without density loss
• Proposes single-transistor XOR encryption using FeFET devices
• Achieves higher throughput and lower latency than AES

Innovation

• Single-transistor FeFET cell enables encryption without density loss.
• In-memory XOR scheme uses threshold voltage for ciphertext encoding.
• Multi-level-cell FeFETs store multiple bits per transistor efficiently.