The BrainScaleS-2 multi-chip system: Interconnecting continuous-time neuromorphic compute substrates

2025-12-03

AI Summary

To address the challenge of achieving efficient inter-chip interconnection for continuous-time neuromorphic computing on the BrainScaleS-2 multi-die system, this work proposes a scalable multi-board interconnect architecture based on FPGAs and custom Aggregator units. The architecture integrates analog neuron/synapse ASICs, Node-FPGA control units, Ethernet communication, and SIMD-enhanced dual CPUs, enabling ultra-low-latency inter-die communication (<1.3 μs) across three FPGAs and four hop stages, while supporting highly scalable brain-inspired computation. Its key innovations include: (i) the first integration of dual interconnect backplanes within a standard 4U rack; and (ii) experimental validation of system stability across diverse spike frequencies. This design significantly improves communication efficiency and scalability for large-scale neuromorphic networks, establishing a scalable interconnect paradigm for real-time, low-latency neuromorphic hardware.

Technology Category

• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Multiagent Systems: Agent Communication
• Machine Learning: Hardware-aware ML

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

The BrainScaleS-2 SoC integrates analog neuron and synapse circuits with digital periphery, including two CPUs with SIMD extensions. Each ASIC is connected to a Node-FPGA, providing experiment control and Ethernet connectivity. This work details the scaling of the compute substrate through FPGA-based interconnection via an additional Aggregator unit. The Aggregator provides up to 12 transceiver links to a backplane of Node-FPGAs, as well as 4 transceiver lanes for further extension. Two such interconnected backplanes are integrated into a standard 19in rack case with 4U height together with an Ethernet switch, system controller and power supplies. For all spike rates, chip-to-chip latencies -- consisting of four hops across three FPGAs -- below 1.3$mu$s are achieved within each backplane.

Problem

• Interconnecting continuous-time neuromorphic compute substrates across chips
• Scaling the compute substrate via FPGA-based interconnection and an Aggregator unit
• Achieving sub-1.3μs chip-to-chip latencies across multiple FPGA hops

Innovation

• Analog-digital neuromorphic SoC with SIMD CPUs
• FPGA-based interconnection via Aggregator unit
• Low-latency multi-chip scaling in rack system