Near-Memory Architecture for Threshold-Ordinal Surface-Based Corner Detection of Event Cameras

2025-12-02

AI Summary

To address high latency and low energy efficiency of Threshold-Ordinal Surface (TOS) corner detection on event-based cameras (EBCs) deployed on edge devices, this work proposes NM-TOS—a near-memory computing architecture. NM-TOS employs a read-write decoupled 8T SRAM cell to enable efficient in-situ updates of the threshold-ordinal surface, integrated with pipelined parallelism, hardware-software co-design, and dynamic voltage and frequency scaling (DVFS). Implemented in 65 nm CMOS technology, it achieves up to 24.7× lower latency and 6.6× lower power consumption versus conventional digital implementations. Monte Carlo simulations confirm robust circuit operation, with corner detection AUC degradation limited to only 0.015–0.027—preserving high accuracy. To our knowledge, this is the first work to introduce near-memory computing to real-time corner detection on EBCs, establishing a new paradigm for low-latency, energy-efficient neuromorphic vision processing.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Computer Vision: Learning & Optimization for CV

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Security and Privacy: Large-scale security measurements

Abstract

Event-based Cameras (EBCs) are widely utilized in surveillance and autonomous driving applications due to their high speed and low power consumption. Corners are essential low-level features in event-driven computer vision, and novel algorithms utilizing event-based representations, such as Threshold-Ordinal Surface (TOS), have been developed for corner detection. However, the implementation of these algorithms on resource-constrained edge devices is hindered by significant latency, undermining the advantages of EBCs. To address this challenge, a near-memory architecture for efficient TOS updates (NM-TOS) is proposed. This architecture employs a read-write decoupled 8T SRAM cell and optimizes patch update speed through pipelining. Hardware-software co-optimized peripheral circuits and dynamic voltage and frequency scaling (DVFS) enable power and latency reductions. Compared to traditional digital implementations, our architecture reduces latency/energy by 24.7x/1.2x at Vdd = 1.2 V or 1.93x/6.6x at Vdd = 0.6 V based on 65nm CMOS process. Monte Carlo simulations confirm robust circuit operation, demonstrating zero bit error rate at operating voltages above 0.62 V, with only 0.2% at 0.61 V and 2.5% at 0.6 V. Corner detection evaluation using precision-recall area under curve (AUC) metrics reveals minor AUC reductions of 0.027 and 0.015 at 0.6 V for two popular EBC datasets.

Problem

• Reduces latency in event-based corner detection on edge devices
• Optimizes power consumption for threshold-ordinal surface algorithms
• Enables efficient near-memory architecture for resource-constrained hardware

Innovation

• Near-memory architecture with 8T SRAM for TOS updates
• Hardware-software co-optimized circuits with DVFS for efficiency
• Pipelined patch updates to reduce latency and energy