MLDSE: Scaling Design Space Exploration Infrastructure for Multi-Level Hardware

2025-03-27

AI Summary

Multi-level hardware design space exploration (DSE) faces fundamental challenges in modeling complex spatial hierarchies, cross-level communication, and architectural polymorphism. To address these, this paper proposes a domain-specific DSE infrastructure for multi-level hardware systems. Our method introduces: (1) a recursive hardware intermediate representation (IR) that uniformly captures heterogeneous multi-level structures; (2) a spatiotemporal mapping IR and associated primitives that explicitly model inter-level dataflow and computation mapping; and (3) a task-level event-driven simulation generation mechanism coupled with a resource-contention-aware, hardware-consistent scheduling algorithm. The framework enables joint DSE across architecture, parameter, and mapping dimensions. Evaluated on large language model workloads, it achieves significant improvements in exploration efficiency and coverage breadth. This work establishes a scalable foundation for systematic, co-designed development of multi-level hardware systems.

Technology Category

• Machine Learning: Hardware-aware ML
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Knowledge Representation and Reasoning: Geometric, Spatial, and Temporal Reasoning

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments
• Graph Algorithms and Modeling for the Web: Algorithms and analysis for heterogeneous, signed, attributed, multi-relational, temporal, higher-order, and annotated Web-related graphs
• Semantics and Knowledge: Data modeling to support human-machine intelligence, including LLMs agents, intelligent system behavior, explanations, and user-friendly interactions

Abstract

To efficiently support large-scale NNs, multi-level hardware, leveraging advanced integration and interconnection technologies, has emerged as a promising solution to counter the slowdown of Moore's law. However, the vast design space of such hardware, coupled with the complexity of their spatial hierarchies and organizations, introduces significant challenges for design space exploration (DSE). Existing DSE tools, which rely on predefined hardware templates to explore parameters for specific architectures, fall short in exploring diverse organizations, spatial hierarchies, and architectural polymorphisms inherent in multi-level hardware. To address these limitations, we present Multi-Level Design Space Exploror (MLDSE), a novel infrastructure for domain-specific DSE of multi-level hardware. MLDSE introduces three key innovations from three basic perspectives of DSE: 1) Modeling: MLDSE introduces a hardware intermediate representation (IR) that can recursively model diverse multi-level hardware with composable elements at various granularities. 2) Mapping: MLDSE provides a comprehensive spatiotemporal mapping IR and mapping primitives, facilitating the mapping strategy exploration on multi-level hardware, especially synchronization and cross-level communication; 3) Simulation: MLDSE supports universal simulator generation based on task-level event-driven simulation mechanism. It features a hardware-consistent scheduling algorithm that can handle general task-level resource contention. Through experiments on LLM workloads, we demonstrate MLDSE's unique capability to perform three-tier DSE spanning architecture, hardware parameter, and mapping.

Problem

• Exploring vast design space of multi-level hardware efficiently
• Addressing limitations of existing DSE tools for diverse architectures
• Optimizing spatiotemporal mapping and synchronization in complex hierarchies

Innovation

• Recursive hardware IR for multi-level modeling
• Spatiotemporal mapping IR for strategy exploration
• Event-driven simulator with resource contention handling