Aquas: Enhancing Domain Specialization through Holistic Hardware-Software Co-Optimization based on MLIR

2025-11-27

AI Summary

Existing RISC-V ASIP frameworks suffer from weak hardware synthesis capability and poor compiler retargetability, hindering domain-specific performance gains. This paper proposes an MLIR-based hardware-software co-optimization framework: (1) a burst DMA engine is designed and integrated with high-level synthesis (HLS) optimizations to enhance automated hardware generation; (2) an e-graph–based retargetable compiler is developed, incorporating a novel matching engine to improve instruction selection efficiency and co-design flexibility. The framework unifies multi-level IR abstractions, enables automatic hardware synthesis, and supports semantic-aware pattern matching. Evaluated on real-world workloads—including point-cloud processing and large language model inference—the framework achieves up to 9.27× end-to-end speedup over state-of-the-art ASIP approaches, demonstrating significant improvements in both synthesis capability and compiler adaptability.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Learning & Optimization for CV
• Search and Optimization: Metareasoning and Metaheuristics

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Search and Retrieval-Augmented AI: Vertical and domain-specific search
• Responsible Web: Machine-in-the-loop, human agency and autonomy

Abstract

Application-Specific Instruction-Set Processors (ASIPs) built on the RISC-V architecture offer specialization opportunities for various applications. However, existing frameworks from the open-source RISC-V ecosystem suffer from limited performance due to restricted hardware synthesis and rigid compiler support. To address these challenges, we introduce Aquas, a holistic hardware-software co-design framework built upon MLIR. Aquas enhances ASIP synthesis with fast memory access capability via a burst DMA engine and advanced high-level synthesis (HLS) optimizations. On the compiler side, we propose an e-graph based retargetable approach with a novel matching engine for efficient instruction matching. Evaluation demonstrates up to 9.27x speedup on real-world workloads, including point cloud processing and LLM inference.

Problem

• Enhances ASIP performance via hardware-software co-optimization
• Addresses limited hardware synthesis and rigid compiler support
• Improves efficiency for workloads like point cloud and LLM inference

Innovation

• Hardware-software co-design framework built on MLIR
• Burst DMA engine and HLS optimizations for fast memory access
• E-graph based retargetable compiler with novel matching engine