3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison

2025-11-27

AI Summary

In STT-MRAM caches, parallel tag-array comparisons induce severe read disturb, significantly degrading reliability. This work is the first to identify and systematically address this issue by proposing selective tag comparison: leveraging low-order tag address bits to proactively predict and skip non-matching entries, thereby dynamically disabling invalid tag accesses—without requiring additional prediction hardware. A low-overhead hardware design is implemented and evaluated using gem5 cycle-accurate simulation. Experimental results show that the method reduces tag-array read-disturb rate by 71.8%, improves mean time to failure by 3.6×, cuts energy consumption by 62.1%, and incurs only 0.38% area overhead—all without compromising cache performance. The key contribution is the first lightweight, precise, prediction-free, proactive interference mitigation mechanism tailored specifically for parallel tag access in STT-MRAM caches.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Distributed Search
• Data Mining & Knowledge Management: Scalability, Parallel & Distributed Systems

Application Category

• Security and Privacy: Large-scale security measurements
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments

Abstract

Recent development in memory technologies has introduced Spin-Transfer Torque Magnetic RAM (STT-MRAM) as the most promising replacement for SRAMs in on-chip cache memories. Besides its lower leakage power, higher density, immunity to radiation-induced particles, and non-volatility, an unintentional bit flip during read operation, referred to as read disturbance error, is a severe reliability challenge in STT-MRAM caches. One major source of read disturbance error in STT-MRAM caches is simultaneous accesses to all tags for parallel comparison operation in a cache set, which has not been addressed in previous work. This paper first demonstrates that high read accesses to tag array extremely increase the read disturbance rate and then proposes a low-cost scheme, so-called Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison (3RSeT), to reduce the error rate by eliminating a significant portion of tag reads. 3RSeT proactively disables the tags that have no chance for hit, using low significant bits of the tags on each access request. Our evaluations using gem5 full-system cycle-accurate simulator show that 3RSeT reduces the read disturbance rate in the tag array by 71.8%, which results in 3.6x improvement in Mean Time To Failure (MTTF). In addition, the energy consumption is reduced by 62.1% without compromising performance and with less than 0.4% area overhead.

Problem

• Reduces read disturbance errors in STT-MRAM caches
• Minimizes tag array accesses to prevent unintentional bit flips
• Improves reliability and energy efficiency without performance loss

Innovation

• Selective tag comparison reduces read disturbance
• Disables unlikely hit tags using low significant bits
• Reduces energy and area overhead without performance loss