AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL

2025-03-24

AI Summary

Automatically translating natural-language specifications into SystemVerilog Assertions (SVAs) faces fundamental challenges—including linguistic ambiguity, specification incompleteness, and absence of RTL semantics. To address these, we propose the first knowledge graph (KG)-based approach that jointly models specification documents and RTL code, featuring a hardware-specific schema and supporting multi-granularity verification context synthesis. Our method deeply integrates the KG throughout the SVA generation pipeline via RTL semantic parsing, domain-specific entity-relation extraction, and LLM prompt enhancement—enabling context-aware assertion generation. Evaluated on four industrial-scale designs, our approach achieves substantial improvements in assertion coverage (+23.6%) and correctness (+31.4%) over state-of-the-art baselines (e.g., AssertLLM), delivering more reliable and interpretable automation for formal verification.

Technology Category

• Knowledge Representation and Reasoning: Automated Reasoning and Theorem Proving
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language

Application Category

• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Search and Retrieval-Augmented AI: Vertical and domain-specific search
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs

Abstract

Generating SystemVerilog Assertions (SVAs) from natural language specifications remains a major challenge in formal verification (FV) due to the inherent ambiguity and incompleteness of specifications. Existing LLM-based approaches, such as AssertLLM, focus on extracting information solely from specification documents, often failing to capture essential internal signal interactions and design details present in the RTL code, leading to incomplete or incorrect assertions. We propose a novel approach that constructs a Knowledge Graph (KG) from both specifications and RTL, using a hardware-specific schema with domain-specific entity and relation types. We create an initial KG from the specification and then systematically fuse it with information extracted from the RTL code, resulting in a unified, comprehensive KG. This combined representation enables a more thorough understanding of the design and allows for a multi-resolution context synthesis process which is designed to extract diverse verification contexts from the KG. Experiments on four designs demonstrate that our method significantly enhances SVA quality over prior methods. This structured representation not only improves FV but also paves the way for future research in tasks like code generation and design understanding.

Problem

• Generating accurate SystemVerilog Assertions from ambiguous specifications
• Capturing RTL signal interactions missing in existing LLM approaches
• Constructing unified Knowledge Graph from specs and RTL for verification

Innovation

• Constructs Knowledge Graph from specs and RTL
• Uses hardware-specific schema for entity relations
• Multi-resolution context synthesis from unified KG