Comparing the Run-time Behavior of Modern PDES Engines on Alternative Hardware Architectures

2025-03-25

AI Summary

Modern parallel discrete-event simulation (PDES) engines exhibit architecture-dependent runtime behavior on heterogeneous NUMA systems, complicating hardware selection and infrastructure investment decisions. Method: We conduct an experimental, NUMA-aware performance evaluation comparing the optimistic USE engine and conservative PARSIR engine across x86 (CISC) and PowerPC (RISC) platforms, using diverse real-world simulation workloads. Contribution/Results: We identify that PDES engine performance is critically sensitive to memory topology and ISA characteristics: USE suffers from high cache-coherence overhead and significant performance variability on x86, whereas PARSIR achieves superior scalability on PowerPC. Based on these findings, we propose a hardware-architecture suitability assessment framework and a cross-platform PDES tuning guideline. This work provides empirical evidence and methodological support for co-designing PDES software and hardware, advancing NUMA-aware simulation system optimization.

Technology Category

• Search and Optimization: Sampling/Simulation-based Search
• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• User Modeling, Personalization and Recommendation: User modeling and simulation for interactive and conversational systems
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

The current trend of technology has brought parallel machines equipped with multiple processors and multiple memory sockets to be available off-the-shelf -- or via renting through Iaas Clouds -- at reasonable costs. This has opened the possibility of natively supporting HPC in diffused realities, like industry or academic labs. At the same time, the Parallel Discrete Event Simulation (PDES) area has given rise to attractive simulation engines, designed with orientation to high performance and scalability, also targeting differentiated exploitation of the specific support offered by the underlying hardware. In this article, we present an experimental study where we deploy two last-generation open-source PDES platforms -- one optimistic (USE) and one conservative (PARSIR) -- on top of two significantly different hardware chipsets based on either {sf x86} CISC or {sf powerPC} RISC technology, both offering multiple Non-Uniform-Memory-Access (NUMA) nodes and multiple tens of cores and hardware-threads (logical CPUs). Also, we consider real-world simulation models configured in a variety of different manners in order to investigate the actual execution profile of the PDES engines on the two distinct hardware platforms. Our objective is the one of providing insights on current performance trends, which can support decisions in terms of both strategies -- for software platforms to adopt -- and investments -- in terms of hardware platforms -- in the area of discrete event simulation.

Problem

• Compare PDES engines on different hardware architectures
• Evaluate performance of optimistic and conservative PDES platforms
• Analyze execution profiles on x86 and powerPC NUMA systems

Innovation

• Deploying PDES engines on x86 and powerPC architectures
• Comparing optimistic (USE) and conservative (PARSIR) platforms
• Analyzing NUMA nodes and multi-core performance