Enabling AI ASICs for Zero Knowledge Proof

2026-04-20

AI Summary

Zero-knowledge proofs (ZKPs) suffer from limited efficiency due to the high computational cost of multi-scalar multiplication (MSM) and number-theoretic transforms (NTT). This work proposes MORPH, a framework that, for the first time, reformulates core ZKP computations to align with the execution model of AI ASICs such as TPUs. By introducing a hardware-aware Big-T complexity model, an MXU-centric extended RNS lazy reduction scheme, and a unified tiling layout strategy, MORPH eliminates carry chains and avoids on-chip data reshuffling. Further optimizations include low-precision GEMM conversion via JAX, an enhanced Pippenger algorithm for MSM, and a 3/5-step NTT design, all tailored to maximize utilization of TPU matrix units. Evaluated on TPUv6e8, the approach achieves up to a 10× increase in NTT throughput and delivers MSM performance on par with specialized ZKP accelerators like GZKP.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Search and Optimization: Learning to Search

Application Category

• Security and Privacy: Data transparency and provenance
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Responsible Web: Data and user privacy-enhancing technologies for the Web

Abstract

Zero-knowledge proof (ZKP) provers remain costly because multi-scalar multiplication (MSM) and number-theoretic transforms (NTTs) dominate runtime as they need significant computation. AI ASICs such as TPUs provide massive matrix throughput and SotA energy efficiency. We present MORPH, the first framework that reformulates ZKP kernels to match AI-ASIC execution. We introduce Big-T complexity, a hardware-aware complexity model that exposes heterogeneous bottlenecks and layout-transformation costs ignored by Big-O. Guided by this analysis, (1) at arithmetic level, MORPH develops an MXU-centric extended-RNS lazy reduction that converts high-precision modular arithmetic into dense low-precision GEMMs, eliminating all carry chains, and (2) at dataflow level, MORPH constructs a unified-sharding layout-stationary TPU Pippenger MSM and optimized 3/5-step NTT that avoid on-TPU shuffles to minimize costly memory reorganization. Implemented in JAX, MORPH enables TPUv6e8 to achieve up-to 10x higher throughput on NTT and comparable throughput on MSM than GZKP. Our code: https://github.com/EfficientPPML/MORPH.

Problem

• Zero-knowledge proof
• Multi-scalar multiplication
• Number-theoretic transform
• AI ASICs
• Computational cost

Innovation

• Zero-Knowledge Proof
• AI ASIC
• Matrix Multiplication Unit (MXU)
• Number-Theoretic Transform
• Multi-Scalar Multiplication