On Solving Structured SAT on Ising Machines: A Semiprime Factorization Study

2025-11-25

AI Summary

This study identifies a fundamental bottleneck in solving structured SAT problems—exemplified by semiprime factorization—on Ising machines: strong logical constraints severely distort Ising dynamics, rendering conventional end-to-end Hamiltonian mappings ineffective. Method: We propose a “constraint-aware hybrid computing architecture” that offloads highly constrained subproblems (e.g., multiplication logic) to classical pre-processing, while delegating only the optimization-dominant components to the Ising hardware. Contribution/Results: This work is the first to systematically identify and circumvent the dynamical mismatch between structured SAT instances and Ising hardware. Experiments on a 45-qubit fully connected Ising chip demonstrate that, without hardware modification, the solvable semiprime bit-width increases from 8 bits (94 variables) to 11 bits (190 variables)—a 2.02× scaling in problem size—thereby substantively extending the practical applicability boundary of Ising-based computing.

Technology Category

• Constraint Satisfaction and Optimization: Satisfiability
• Machine Learning: Hardware-aware ML
• Search and Optimization: Mixed Discrete/Continuous Search

Application Category

• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Semantics and Knowledge: Data modeling to support human-machine intelligence, including LLMs agents, intelligent system behavior, explanations, and user-friendly interactions
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs

Abstract

Ising machines are emerging as a new technology for solving various classes of computationally hard problems of practical importance, yet their limits on structured SAT workloads, representative of numerous real-world applications, remain unexplored. We present the first systematic study of such problems, using semiprime factorization as a representative case. Our results show that highly restrictive, 'tight' constraints, when mapped into optimization form, fundamentally distort Ising dynamics, and that these distortions are amplified when problems are decomposed to fit within limited hardware. We propose a hybrid approach that offloads constraint-heavy components to classical preprocessing while reserving the computationally challenging part for the Ising machine. Structured SAT represents a crucial step toward real-world applications, which remain out of reach today due to Ising machine limitations. Our findings reveal that constraint handling is a central obstacle and highlight hybrid hardware-software approaches as the path forward to unlocking the long-term potential of Ising machines. We conduct our evaluation on the manufactured Ising chips and demonstrate that our flow more than doubles the solvable problem size on a 45-spin all-to-all Ising chip, from 8-bit (94 variables) to 11-bit (190 variables), without hardware changes.

Problem

• Investigating Ising machine limitations on structured SAT problems
• Analyzing constraint-induced distortions in semiprime factorization mapping
• Developing hybrid approaches to overcome hardware constraints

Innovation

• Hybrid classical-Ising constraint preprocessing approach
• Decomposition method for limited hardware capacity
• Constraint-heavy components offloaded to classical solvers