A Jammer-Resilient 2.87 mm$^2$ 1.28 MS/s 310 mW Multi-Antenna Synchronization ASIC in 65 nm

2025-11-26

AI Summary

To address the robustness bottleneck of multi-antenna time synchronization systems under intelligent jamming attacks, this work proposes and implements the first application-specific integrated circuit (ASIC) dedicated to anti-jamming time synchronization. The ASIC enables high-precision synchronization between a single-antenna transmitter and a 16-antenna receiver, and—uniquely at the hardware level—integrates a spatio-temporal joint anti-jamming algorithm capable of effectively suppressing up to two coordinated intelligent jammers. Fabricated in 65 nm CMOS, the core die occupies 2.87 mm² and consumes 310 mW. Operating at a 1.28 MS/s sampling rate, it delivers fully pipelined, real-time synchronization processing. Experimental evaluation demonstrates nanosecond-level synchronization accuracy even under strong jamming conditions, significantly enhancing both the security and engineering practicality of time synchronization systems.

Technology Category

• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Machine Learning: Hardware-aware ML
• Intelligent Robots: Multi-Robot Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Security and Privacy: Applications of cryptography
• Search and Retrieval-Augmented AI: Agentic search

Abstract

We present the first ASIC implementation of jammer-resilient multi-antenna time synchronization. The ASIC implements a recent algorithm that mitigates jamming attacks on synchronization signals using multi-antenna processing. Our design supports synchronization between a single-antenna transmitter and a 16-antenna receiver while mitigating smart jammers with up to two transmit antennas. The fabricated 65 nm ASIC has a core area of 2.87 mm$^2$, consumes a power of 310 mW, and supports a sampling rate of 1.28 mega-samples per second (MS/s).

Problem

• Mitigating jamming attacks on synchronization signals
• Implementing multi-antenna processing for time synchronization
• Supporting synchronization between single-antenna transmitter and 16-antenna receiver

Innovation

• Multi-antenna processing mitigates jamming attacks
• ASIC supports single to 16-antenna synchronization
• 65 nm chip achieves 1.28 MS/s sampling rate