A 0.32 mm$^2$ 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection

2025-11-26

AI Summary

To address the performance degradation of SIMO receivers under intelligent/broadband interference, this work proposes and implements the world’s first single-chip ASIC integrating interference suppression, channel estimation, and data detection. We introduce the MAED (Multi-Antenna Estimation and Detection) joint signal processing algorithm, which unifies interference cancellation and parameter estimation via spatial filtering and supports up to eight receive antennas. Fabricated in 22-nm fully depleted silicon-on-insulator (FD-SOI) technology, the chip employs a nonlinear optimization architecture to achieve 100 Mb/s throughput within a compact 0.32 mm² core area and 223 mW power consumption. Compared to state-of-the-art solutions, the design delivers a 3× improvement in user throughput and a 4.5× gain in area efficiency, significantly enhancing communication robustness and energy efficiency in highly interfered environments.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Sampling/Simulation-based Search
• Multiagent Systems: Mechanism Design

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Data management and stream processing for Web, mobile and wireless applications
• Security and Privacy: Large-scale security measurements
• User Modeling, Personalization and Recommendation: On-Device user modeling, personalization, and recommendation

Abstract

We present the first single-input multiple-output (SIMO) receiver ASIC that jointly performs jammer mitigation, channel estimation, and data detection. The ASIC implements a recent algorithm called siMultaneous mitigAtion, Estimation, and Detection (MAED). MAED mitigates smart jammers via spatial filtering using a nonlinear optimization problem that unifies jammer estimation and nulling, channel estimation, and data detection to achieve state-of-the-art error-rate performance under jamming. The design supports eight receive antennas and enables mitigation of smart jammers as well as of barrage jammers. The ASIC is fabricated in 22 nm FD-SOI, has a core area of 0.32 mm$^2$, and achieves a throughput of 100 Mb/s at 223 mW, thus delivering 3$ imes$ higher per-user throughput and 4.5$ imes$ higher area efficiency than the state-of-the-art jammer-resilient detector.

Problem

• Jointly mitigates jammers, estimates channels, and detects data
• Enables resilient communication under smart and barrage jammers
• Achieves high throughput and area efficiency in SIMO systems

Innovation

• Joint jammer mitigation channel estimation data detection
• Spatial filtering via nonlinear optimization problem
• Eight receive antennas mitigate smart barrage jammers